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CS42436 датащи(PDF) 36 Page - Cirrus Logic |
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CS42436 датащи(HTML) 36 Page - Cirrus Logic |
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36 / 66 page ![]() 36 DS647PP2 5.6 AUX Port Digital Interface Formats These serial data lines are used when supporting the TDM Mode of operation with an external ADC or S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will op- erate at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN signal is not being used, it should be tied to AGND via a pull-down resistor. Hardware Mode The AUX port will only operate in the Left Justified digital interface format and supports bit depths ranging from 16 to 24 bits (see figure 16 on page 36 for timing relationship between AUX_LRCK and AUX_SCLK). Software Mode The AUX port will operate in either the Left Justified or I²S digital interface format with bit depths ranging from 16 to 24 bits. Settings for the AUX port are made through the register “Miscellaneous Control (ad- dress 04h)” on page 45. 5.6.1 I²S 5.6.2 Left Justified AUX_LRCK AUX_SCLK MS B LS B MS B LS B AUX1 Left C h an ne l R ig h t C h an n e l AUX_SDIN AUX2 MSB Figure 15. AUX I²S Format AUX_LRCK AUX_SCLK MS B LS B MS B LS B AUX1 L e ft C hanne l R ig h t C han ne l AUX_SDIN AUX2 MSB Figure 16. AUX Left Justified Format |
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