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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS42436 датащи(PDF) 29 Page - Cirrus Logic |
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CS42436 датащи(HTML) 29 Page - Cirrus Logic |
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29 / 66 page  DS647PP2 29 5.2.2 ADC3 Analog Input ADC3 accommodates differential as well as single-ended inputs. In Single-Ended mode, an in- ternal MUX selects from up to 4 single-ended inputs. Hardware Mode Single-Ended mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup. Analog input selection is then made via the AINx_MUX pins. See Tables 3-4 below for ADC3 setup options. Refer to Figure 10 on page 29 for the internal ADC3 analog input topology. Full-Scale Differential Input Level = (AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS AINx+ AINx- 3.9 V 2.5 V 1.1 V 5.0 V 3.9 V 2.5 V 1.1 V VA Figure 9. Full-Scale Input AIN5 + - AIN5_MUX VQ AIN6_MUX VQ ADC3 Single-Ended Input Filter Single-Ended Input Filter Single-Ended Input Filter Single-Ended Input Filter Differential Input Filter 50 49 52 51 ADC3 SINGLE Differential Input Filter AIN5A AIN5B AIN5+/- AIN6+/- AIN6A AIN6B 1 0 1 0 1 0 0 1 AIN6 + - 1 0 0 1 Figure 10. ADC3 Input Topology |
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