CS42428 datasheet(38/67 Pages) CIRRUS

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CS42428

5.7.2

OMCK FREQUENCY (OMCK FREQX)

Default = 00

Function:

Sets the appropriate frequency for the supplied OMCK.

5.7.3

PLL LOCK TO LRCK (PLL_LRCK)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, the internal PLL of the CS42428 will lock to the LRCK of the ADC serial port

(ADC_LRCK) while the ADC_SP is in slave mode.

5.7.4

MASTER CLOCK SOURCE SELECT (SW_CTRLX)

Default = 01

Function:

These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)”

on page 46, determine the master clock source for the CS42428. When SW_CTRL1 and SW_CTRL0

are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes

unlocked, then RMCK will equal OMCK, but all internal and serial port timings are not valid.

5.7.5

FORCE PLL LOCK (FRC_PLL_LK)

Default = 0

Function:

This bit is used to enable the PLL to lock to the ADC_LRCK with the absence of a clock signal on

OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will be disabled. The OM-

CK/PLL_CLK Ratio (address 07h) (Read Only) register contents are not valid and the PLL_CLK[2:0]

bits will be set to ‘111’b. Use the DE-EMPH[1:0] bits to properly apply de-emphasis filtering.

OMCK Freq1 OMCK Freq0 Description

11.2896 MHz or 12.2880 MHz

16.9344 MHz or 18.4320 MHz

22.5792 MHz or 24.5760 MHz

Reserved

Table 11. OMCK Frequency Settings

SW_CTRL1 SW_CTRL0

UNLOCK

Description

Manual setting, MCLK sourced from

PLL.

Manual setting, MCLK sourced from OMCK.

Hold, keep same MCLK source.

Auto switch, MCLK sourced from OMCK.

Auto switch, MCLK sourced from PLL.

Auto switch, MCLK sourced from OMCK.

Table 12. Master Clock Source Select

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