CS42418 datasheet(23/67 Pages) CIRRUS

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CS42418

3.5.4.2

OLM Config #2

This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and will handle up

to 20-bit samples at a sampling frequency of 96 kHz on all channels for both the DAC and ADC. The out-

put data stream of the internal and external ADCs is configured to use the ADC_SDOUT output and run

at the DAC Serial Port sample frequency.

Description

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

DAC_LRCK can run at SSM, DSM or QSM independent of ADC_LRCK

Set ADC_FMx = 00,01,10

ADC_LRCK can run at SSM, DSM or QSM independent of DAC_LRCK

Set ADC_CLK_SEL = 1

Configure ADC_SDOUT to be clocked from the ADC_SP clocks.

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Select the digital interface format when not in one line mode

Set ADC_OLx bits = 00,01,10

Select ADC operating mode, see table below for valid combinations

Set DAC_OLx bits = 00,01

Select DAC operating mode, see table below for valid combinations

Misc. Control Register (addr = 05h)

Set CODEC_SP M/S = 1

Set CODEC Serial Port to master mode.

Set SAI_SP M/S = 1

Set Serial Audio Interface Port to master mode.

Set EXT ADC SCLK = 1

Identify external ADC clock source as DAC Serial Port.

DAC Mode

Not One Line Mode

One Line Mode #1

One Line Mode #2

ADC Mode

Not One

Line Mode

DAC_SCLK=64Fs

DAC_LRCK=SSM/DSM/QSM

ADC_SCLK=64Fs

ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs

DAC_LRCK=SSM

ADC_SCLK=64Fs

ADC_LRCK=SSM/DSM/QSM

not valid

One Line

Mode #1

DAC_SCLK=64Fs

DAC_LRCK=SSM/DSM

ADC_SCLK=128Fs

ADC_LRCK=CX_LRCK

DAC_SCLK=128Fs

DAC_LRCK=SSM

ADC_SCLK=128Fs

ADC_LRCK=CX_LRCK

not valid

One Line

Mode #2

DAC_SCLK=64Fs

DAC_LRCK=SSM

ADC_SCLK=256Fs

ADC_LRCK=CX_LRCK

not valid

SC LK_PO RT1

LRC K_PO R T1

SD IN _PO R T1

SC LK_PO RT2

LRC K_P OR T2

SD OUT1_PORT2

SD OUT2_PORT2

SD OUT3_PORT2

SD OUT4_PORT2

RMCK

ADC IN1

ADC IN2

MCLK

SDO UT1

SDO UT2

LRCK

SCLK

64Fs,128Fs

ADC Data

64Fs ,128Fs,

256Fs

DIGITA L AUD IO

PROCESSOR

CS5361

C S5361

AD C_SCLK

ADC_LRCK

AD C_S DO UT

DA C_S CLK

D AC_LRCK

DAC _SD IN1

DAC _SD IN2

DAC _SD IN3

DAC _SD IN4

MCLK

Figure 14. OLM Configuration #2

CS42418

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