CS42418 datasheet(61/67 Pages) CIRRUS

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CS42418

SWITCHING CHARACTERISTICS (For CQ, T

A = -10 to +70° C; For DQ, TA = -40 to +85° C;

VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, CL = 30 pF)

Notes: 13. After powering up the CS42418, RST should be held low after the power supplies and clocks are settled.

14. See Table 2 on page 15 for suggested OMCK frequencies

15. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.

Parameters

Symbol

Min

Typ

Max

Units

RST pin Low Pulse Width

(Note 13)

PLL Clock Recovery Sample Rate Range

200

kHz

RMCK output jitter

(Note 15)

200

ps RMS

RMCK output duty cycle

OMCK Duty Cycle

(Note 14)

DAC_SCLK, ADC_SCLK Duty Cycle

DAC_LRCK, ADC_LRCK Duty Cycle

Master Mode

RMCK to DAC_SCLK, ADC_SCLK active edge delay

tsmd

RMCK to DAC_LRCK, ADC_LRCK delay

tlmd

Slave Mode

DAC_SCLK, ADC_SCLK Falling Edge to

ADC_SDOUT, ADC_SDOUT Output Valid

tdpd

-50

DAC_LRCK, ADC_LRCK Edge to MSB Valid

tlrpd

-20

DAC_SDIN Setup Time Before DAC_SCLK Rising

Edge

tds

-10

DAC_SDIN Hold Time After DAC_SCLK Rising Edge

tdh

-30

DAC_SCLK, ADC_SCLK High Time

tsckh

DAC_SCLK, ADC_SCLK Low Time

tsckl

DAC_SCLK, ADC_SCLK rising to DAC_LRCK,

SAI_LRCK Edge

tlrckd

DAC_LRCK, ADC_LRCK Edge to DAC_SCLK,

ADC_SCLK Rising

tlrcks

DAC_SCLK

ADC_SCLK

(output)

RM CK

smd

lmd

DAC_LRCK

ADC_LRCK

(output)

sckh

sckl

MSB

MS B-1

tdpd

ADC _ SD OU T

DAC _S DIN x

lrpd

lrcks

lrckd

DA C_ SC LK

AD C_ SC LK

(in put)

DA C_ LR CK

AD C_ LR CK

(inp ut)

Figure 56. Serial Audio Port Master Mode Timing

Figure 57. Serial Audio Port Slave Mode Timing

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