CS8427-CSZ datasheet(30/59 Pages) CIRRUS

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CS8427

DS477F3

SPD1:SPD0 - Serial Audio Output Port Data Source

Default = ‘10’

00 - Reserved

01 - Serial Audio Input Port

10 - AES3 receiver

11 - Reserved

11.4 Clock Source Control (04h)

This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-

ious Receiver/Transmitter/Transceiver modes may be selected.

RUN - Controls the internal clocks, allowing the CS8427 to be placed in a “powered down”, low current consumption,

state.

Default = ‘0’

0 - Internal clocks are stopped. Internal state machines are reset. The fully static

control port is operational, allowing registers to be read or changed. Reading and

writing the U and C data buffers is not possible. Power consumption is low.

1 - Normal part operation. This bit must be written to the 1 state to allow the CS8427

to begin operation. All input clocks should be stable in frequency and phase when

RUN is set to 1.

CLK1:0 - Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits

are changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start

the CS8427 (RUN = 1).

Default = ‘00’

00 - OMCK frequency is 256 * Fso

01 - OMCK frequency is 384 * Fso

10 - OMCK frequency is 512 * Fso

11 - Reserved

OUTC - Output Time Base

Default = ‘0’

0 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.

1 - Recovered Input Clock

INC - Input Time Base Clock Source

Default = ‘0’

0 - Recovered Input Clock

1 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.

RXD1:0 - Recovered Input Clock Source

Default = ‘00’

00 - 256 * Fsi, where Fsi is derived from the ILRCK pin (only possible when the

serial audio input port is in slave mode)

01 - 256 * Fsi, where Fsi is derived from the AES3 input frame rate

10 - Bypass the PLL and apply an external 256 * Fsi clock through the RMCK pin. The AES3

receiver is held in synchronous reset. This setting is useful to prevent UNLOCK

interrupts when using an external RMCK and inputting data through the serial audio input port.

11 - Reserved.

RUN

CLK1

CLK0

OUTC

INC

RXD1

RXD0

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