CS8427-CSZ datasheet(56/59 Pages) CIRRUS

56 / 59 page

CS8427

DS477F3

19.3

Component Value Selection

When transitioning from one revision of the part

another, component values may need to be

changed. While it is mandatory for customers to

change the external PLL component values when

transitioning from revision A to revision A1 or from

revision A to revision A2, customers do not need to

change external PLL component values when tran-

sitioning from revision A1 to revision A2, unless the

part is used in an application that is required to

pass the AES3 or IEC60958-4 specification for re-

ceiver jitter tolerance (see Table 7).

19.3.1

Identifying the Part Revision

The first line of the part marking on the package in-

dicates the part number and package type

(CS8427-xx). Table 5 shows a list of part revisions

and their corresponding second line part marking,

which indicates what revision the part is.

19.3.2

Locking to the RXP/RXN Receiver

Inputs

CS8427 parts that are configured to lock to only

the RXP/RXN receiver inputs should use the exter-

nal PLL component values listed in Table 6 and

Table 7. Values listed for the 32 to 96 kHz Fs

range will have the highest corner frequency jitter

attenuation curve, take the shortest time to lock,

and offer the best output jitter performance.

Revision

Pre-October 2002

SOIC & TSSOP (10-Digit)

New SOIC

(12-Digit)

New TSSOP

(10-Digit)

Zxxxxxxxxx

ZFBAAXxxxxxx

NAAXxxxxxx

Rxxxxxxxxx

RFBAA1xxxxxx

NAA1xxxxxx

N/A

RFBAA2xxxxxx

NAA2xxxxxx

Table 5. Second Line Part Marking

Revision

RFILT (kΩ)CFILT (µF)

CRIP (nF)

PLL Lock Time (ms)

0.909

1.8

0.4

0.47

0.4

0.47

Table 6. Locking to RXP/RXN - Fs = 8 to 96 kHz

Revision

RFILT (kΩ)CFILT (µF)

CRIP (nF)

PLL Lock Time (ms)

3.0

0.047

2.2

A1*

1.2

0.1

4.7

1.2

0.1

4.7

A2*

1.6

0.33

4.7

Table 7. Locking to RXP/RXN - Fs = 32 to 96 kHz

* Parts used in applications that are required to pass the AES3 or IEC60958-4 specification for re-

ceiver jitter tolerance should use these component values. Please note that the AES3 and IEC60958

specifications do not have allowances for locking to sample rates less than 32 kHz or for locking to

the ILRCK input. Also note that many factors can affect jitter performance in a system. Please follow

the circuit and layout recommendations outlined previously.

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