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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS8427-CSZ датащи(PDF) 58 Page - Cirrus Logic |
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CS8427-CSZ датащи(HTML) 58 Page - Cirrus Logic |
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58 / 59 page  CS8427 58 DS477F3 19.3.5 Jitter Attenuation Shown in Figure 33, Figure 34, Figure 35, and Fig- ure 36 are jitter attenuation plots for the various re- visions of the CS8427 when used with the appropriate external PLL component values (as noted in Table 7). The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than 32 kHz or for locking to the ILRCK input. These specifications state a max- imum of 2 dB jitter gain or peaking. 10 −1 10 0 10 1 10 2 10 3 10 4 10 5 −20 −15 −10 −5 0 5 Jitter Frequency (Hz) 10 −1 10 0 10 1 10 2 10 3 10 4 10 5 −20 −15 −10 −5 0 5 Jitter Frequency (Hz) 10 −1 10 0 10 1 10 2 10 3 10 4 10 5 −25 −20 −15 −10 −5 0 5 Jitter Frequency (Hz) 10 −1 10 0 10 1 10 2 10 3 10 4 10 5 −25 −20 −15 −10 −5 0 5 Jitter Frequency (Hz) Figure 33. Revision A Figure 34. Revision A1 Figure 35. Revision A2 using A1 values Figure 36. Revision A2 using A2* values |
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