CS7666 datasheet(14/42 Pages) CIRRUS

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CS7666

DS302PP1

In 20-bit wide mode, the luminance information is

output on DOA[9:0] and the chrominance informa-

tion is output on DOB[9:0].

The CS7666 supports both 8-bit and 10-bit opera-

tion as per the ITU-656 recommendation. The ITU-

656 recommendation defines the primary data path

as 8-bits wide with two additional fractional bits

that can be used to form a 10-bit data path. If only

8-bits of output data are used, the two LSBs, DOA1

and DOA0 (DOB1, DOB0) are not used. However,

DOA[9:2] (DOB[9:2]) are connected exactly the

same as in a 10-bit system. This is essential to

properly pass the image data and synchronization

signals to the next component.

Internal Horizontal Scaler

The internal horizontal scaler is used to bridge be-

tween common CCD imager formats and computer

or television formats. In the CS7665 compatibility

mode (default after reset) a 4:5 data rate scaler is

selected by setting the INTERP pin (pin 54 on the

CS7666) to a logical one. The 4:5 scaler will con-

vert a standard 512 horizontal pixel width CCD im-

ager used for cam-corders into the VGA 640x480

format. The CS7615 (if that device is used in the

system) must also have its INTERP pin set high.

When the CS7666 is in the native CS7666 mode

(True_7666 in register 04h set to 1), the INTERP

pin is ignored and the internal scaling ratio is pro-

grammed by the user. The CS7615 must have its

INTERP pin tied to ground.

Several pre-defined scaler modes may be selected

by writing a 3-bit value to bits 0-2 of register 04h.

These default scaling modes are described in

Table 7. If the CUSTOM bit (bit 3 of register 04h)

is set to a 1, then the scaling ratio is determined by

the M and N values contained in the Scaler Control

registers (2Dh - 2Fh.)

CLKIN and CLKIN2X Input Timing

The CLKIN, pin 55, will always require a primary

pixel rate clock source. CCD manufacturers gener-

ally specify a pixel clock frequency that is compat-

Parallel

INTERL = 1

Interleaved

INTERL = 0

DOA[9:0]

10-Bit

Luminance Data

Interleaved 10-Bit

Luminance Data

and 10-Bit

Chrominance Data

DOB[9:0]

10-Bit

Chrominance Data

CLKOUT

Pixel Rate

2x Pixel Rate

Table 5. INTERL Controlled Output Formats

bit 4

Pin 54

Operation

Scaling Ratio

CS7665 mode

1:1

CS7665 mode

4:5

CS7666 mode programmable

Table 6. INTERP Pin (Pin 54)

Mode

CCD Format

CCD Clock (MHz)

Output Format

Input Clock (MHz)

Scaling Ratio

000

CCD

½ input clock

same as CCD

(30 MHz max.)

1:1

001

512x480

9.818

640x480

24.5454

4:5

010

512x480

9.346

720x480

27.000

9:13

011

512x576

9.281

720x480

27.000

11:16

100

362x480

6.75

640x480

24.5454

11:20

101

362x480

6.75

720x480

27.000

1:2

362x576

6.75

720x576

27.000

110

512x576

9.563

720x576

27.000

17:24

111

512x480

9.000

720x480

27.000

2:3

512x576

9.000

720x576

27.000

Table 7. Default Scaling Modes (Register 04h)

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