CS7666 datasheet(10/42 Pages) CIRRUS

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CS7666

DS302PP1

Embedded ITU-656 EAV and SAV Timing

The lines in Figure 3 are numbered 1 through 525.

Video data is not present on lines 1 to 19 or 264 to

282, which constitute the vertical blanking periods.

The vertical blanking is in full line increments,

where Y samples are set to 10h, while Cb and Cr

samples are set to 80h. The interval starting with

EAV and ending with SAV is the digital horizontal

synchronization, which occurs on every line.

It is implicit that the timing reference signals are

contiguous with the video data and continue

through the vertical blanking interval. Each timing

reference signal consists of the four-word sequence

in Table 2. The first three words are a preamble,

followed by a fourth word indicating a) even field

(field 2) identification, b) state of vertical blanking,

and c) state of horizontal blanking. Table 1 details

the timing reference format. The protected bit

states are dependent on the F, V, and H bits accord-

ing to Table 3.

Protected State Bits - In Tables 3 and 4, H, V, and

F bits provide all the necessary timing and state in-

formation. Bits 0 to 3 provide error detection and

correction information. The protection bits allow

for correction of single-bit errors and detection of

two-bit errors. The F or field bit indicates which of

the interlaced fields is active, the first/odd field

which contains 262 lines, or the second/even field

which contains 263 lines.

Value

Description

First Byte

FFh

Fixed

Second Byte

00h

Fixed

Third Byte

00h

Fixed

Fourth Byte

xyh

See Table 3

Table 2. Timing Reference Signal

Bit Position

Word 1281

and 1556

Word 1281

and 1557

Word 1282

and 1558

Word 1283

and 1589

Description

1001

Fixed

F = 0 during Field 1/ODDF = 1

during Field 2/EVEN

V = 0 during Active VideoV = 1

during Vertical Blanking

H = 1 at end of Active VideoH = 0

at start of Active Video

see Protected Bits State Table 4

Table 3. EAV and SAV Timing Reference Signal Detail.

Bit 7

Bit 6 (F)

Bit 5 (V)

Bit 4 (H)

Bit 3 (P3)

Bit 2 (P2)

Bit 1 (P1)

Bit 0 (P0)

0000000

0011101

0101011

0110110

1000111

1011010

1101100

1110001

Table 4. EAV and SAV Protected Bit States Detail.

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