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Low Voltage CMOS Logic – 74LVC2G66

Rev 1.0

29/06/19

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

5

UNITS

1.8 ±0.15V

2

2

2

ns

2.5 ±0.2V

1.2

1.2

1.2

ns

3.3 ±0.3V

0.8

0.8

0.8

ns

Propagation

Delay,

Input A or B

to

Output B or A

8

5 ±0.5V

0.6

0.6

0.6

ns

7. Not production tested in die form, characterized by chip design and tested in package 8. The propagation delay is the calculated RC time constant

of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

6

UNITS

Off-State

Switch

Leakage

Current

5.5V

±0.1

±0.2

±0.2

µA

On-State

Switch

Leakage

Current

5.5V

or GND,

±0.1

±1

±1

µA

Enable Input

Current

5.5V

or GND,

±0.1

±1

±1

µA

Supply

Current

5.5V

or GND

1

1

1

µA

Additional

Supply

Current

5.5V

One input at

other inputs

500

500

500

µA

TYPICAL

Enable Input

Capacitance

5V

3.5

6

Switch

Input/Output

Capacitance

5V

14

pF

1.8V

8

2.5V

9

3.3V

9.5

Power

Dissipation

Capacitance

5V

f = 10MHz,

11

pF