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STR720RXH6 датащи(PDF) 31 Page - STMicroelectronics |
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STR720RXH6 датащи(HTML) 31 Page - STMicroelectronics |
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31 / 401 page ![]() STR720 - ARCHITECTURE OVERVIEW 31/401 Interrupt Vector 12 • CAN Interface interrupt request. Thirty-two different interrupt requests are OR-ed together to generate a single interrupt request: • Status interrupt • Message object 1 to 32 reception/transmission interrupts Interrupt Vector 13 • Buffered SPI 1 interrupt request. Five different interrupt requests are OR-ed together to generate a single interrupt request: • Receive interrupt • Receive overflow • Transmit interrupt • Transmit underflow • Bus error Interrupt Vector 14 • Buffered SPI 2 interrupt request (see Interrupt Vector 13). Interrupt Vectors 15 • Primary IDE interface interrupt request. Interrupt Vectors 16 • Real-Time Clock periodic interrupt request. Interrupt Vector 23 • Analog to Digital Converter sample ready interrupt request. Interrupt Vector 29 • Extended Function Timer 2 output compare A interrupt request. Interrupt Vector 30 • Extended Function Timer 2 output compare B interrupt request. Interrupt Vector 31 • Watchdog Timer interrupt request. 1 |
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