STR720RXH6 datasheet(84/401 Pages) STMICROELECTRONICS

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STR720 - DMA CONTROLLER (DMAC)

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set. This tells the DMA Controller that data stream 3 is now configured for an internal, rather

than an external, transfer request. An internal data transfer consists of two phases: phase 0

(where internal request 0 is asserted) is used for the memory to FIFO data transfer and phase

1 (where internal request 1 is asserted) is used for the FIFO to memory data transfer. An

internal transfer will begin once the ‘Mem2Mem’ bit in the control register is set and data

stream 3 is enabled, provided there are no pending requests for any of the other data streams,

which all have higher priority. If there are pending requests, then these will be serviced first.

When no other requests are pending, phase 0 will start as soon as the channel FIFO can

accept the next data burst from the source address. The data packet size is defined in the

data stream configuration registers. Phase 1 is asserted if the channel FIFO contains enough

data for a next data burst to be sent to the destination address.

Phase 1 will be also started in order to flush the FIFO contents if any of the following

conditions occur:

•

If the terminal count reaches zero this indicates that the FIFO has received the total

number of bytes to be transferred to the destination address. Since this number may

be not a integer multiple of the selected burst size, bytes remaining in the FIFO after

terminal count reaches zero must be flushed to the destination address.

•

If stream 3 is disabled (via a write to the enable bit of the control register for this data

stream).

9.3.1

Circular mode operations

In circular buffer mode, the DMA controller reloads the start address when the word counter

(Terminal Count register) reaches the end of count and continues the transfer until application

software sets the LAST bit, writing into DMALUBuff register the buffer location where the last

data to be transferred is located. The stream configured in circular mode is controlled by a

CIRCULAR flag in DMACtrl register (‘0’=normal mode, ‘1’=circular mode), a LAST flag in

DMALast register (‘0’=infinite mode, ‘1’=last buffer sweep), and a register DMALUBuff (read

and write).

Regarding the usage of circular buffer mode when circular buffer is the source of transfer,

application software should operate in the following way:

1. Set DMA stream configuration registers writing CIRCULAR bit to’1’ and LAST bit to ‘0’.

2. Proceed feeding the circular buffer using an index to keep trace of last buffer location

used.

3. When the end of transfer condition occurs, write DMALUBuff with the value of the index

and set LAST bit to ‘1’.

4. The DMA interrupt line will be activated as soon as DMALUBuff location has been cor-

rectly transferred.

In case circular buffer is the destination of transfer, application should proceed in a similar

way:

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