PRE-BIAS LOAD STARTUP

Should the LM2696 start into a pre-biased load the output

will not be pulled low. This is because the part is asynchro-

nous and cannot sink current. The part will respond to a

pre-biased load by simply enabling PWM high or extending

the off-time until regulation is achieved. This is to say that if

the output voltage is greater than the regulation voltage the

off-time will extend until the voltage discharges through the

feedback resistors. If the load voltage is greater than the

regulation voltage, a series of pulses will charge the output

capacitor to its regulation voltage.

THERMAL CONSIDERATIONS

The thermal characteristics of the LM2696 are specified

using the parameter

θ

ture to the ambient temperature. While the value of

θ

specific to a given set of test parameters (including board

thickness, number of layers, orientation, etc), it provides the

user with a common point of reference.

To obtain an estimate of a devices junction temperature, one

may use the following relationship:

T

θ

Where:

T

P

θ

T

LAYOUT CONSIDERATIONS

The LM2696 regulation and under-voltage comparators are

very fast and will respond to short duration noise pulses.

Layout considerations are therefore critical for optimum per-

formance. The components at pins 5, 6, 7, 12 and 13 should

be as physically close as possible to the IC, thereby mini-

mizing noise pickup in the PC traces. If the internal dissipa-

tion of the LM2696 produces excessive junction tempera-

tures during normal operation, good use of the PC board’s

ground plane can help considerably to dissipate heat. The

exposed pad on the bottom of the TSSOP-16 package can

be soldered to a ground plane on the PC board, and that

plane should extend out from beneath the IC to help dissi-

pate the heat. Use of several vias beneath the part is also an

effective method of conducting heat. Additionally, the use of

wide PC board traces, where possible, can also help con-

duct heat away from the IC. Judicious positioning of the PC

board within the end product, along with use of any available

air flow (forced or natural convection) can help reduce the

junction temperatures. Traces in the power plane (Figure 9)

should be short and wide to minimize the trace impedance;

they should also occupy the smallest area that is reasonable

to minimize EMI. Sizing the power plane traces is a tradeoff

between current capacity, inductance, and thermal dissipa-

tion. For more information on layout considerations, please

refer to National Semiconductor Application Note AN-1229.

20153450

FIGURE 9. Bold Traces Are In The Power Plane

www.national.com

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