DAC5687IPZP datasheet(10/72 Pages) TI

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CLK2

* 0.5 ns

DAC5687

SLWS164B – FEBRUARY 2005 – REVISED JUNE 2005

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,

DVDD = 1.8 V, IOUT

FS = 19.2 mA (unless otherwise noted)

DIGITAL SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PLL

At 600-kHz offset, measured at DAC output,

25 MHz 0-dBFS tone, FDATA = 125 MSPS,

133

dBc/Hz

4x interpolation, pll_freq = 1, pll_kv = 0

Phase noise

At 6-MHz offset, measured at DAC output,

25 MHz 0-dBFS tone, 125 MSPS,

148.5

dBc/Hz

4x interpolation, pll_freq = 1, pll_kv = 0

pll_freq = 0, pll_kv = 0

370

pll_freq = 0, pll_kv = 1

480

VCO maximum frequency

MHz

pll_freq = 1, pll_kv = 0

495

pll_freq = 1, pll_kv = 1

520

pll_freq = 0, pll_kv = 0

225

pll_freq = 0, pll_kv = 1

200

VCO minimum frequency

MHz

pll_freq = 1, pll_kv = 0

480

pll_freq = 1, pll_kv = 1

480

NCO and QMC BLOCKS

QMC clock rate

320

MHz

NCO clock rate

320

MHz

SERIAL PORT TIMING

ts(SDENB)

Setup time, SDENB to rising edge of SCLK

Setup time, SDIO valid to rising edge of

ts(SDIO)

SCLK

Hold time, SDIO valid to rising edge of

th(SDIO)

SCLK

tSCLK

Period of SCLK

100

tSCLKH

High time of SCLK

tSCLK

Low time of SCLK

td(Data)

Data output delay after falling edge of SCLK

CLOCK INPUT (CLK1/CLK1C, CLK2/CLK2C)

Duty cycle

40%

60%

Differential voltage

0.4

TIMING PARALLEL DATA INPUT: CLK1 LATCHING MODES

(PLL Mode –Figure 45, Dual Clock Mode FIFO Disabled – See Figure 47, Dual Clock Mode With FIFO Enabled – See Figure 48)

Setup time, DATA valid to rising edge of

ts(DATA)

0.5

CLK1

Hold time, DATA valid after rising edge of

th(DATA)

1.5

CLK1

Maximum offset between CLK1 and CLK2

t_align

rising edges – Dual Clock Mode with FIFO

disabled

Timing Parallel Data Input (External Clock Mode, Latch on PLLLock Rising Edge, CLK2 Clock Input, See Figure 43 )

Setup time, DATA valid to rising edge of

ts(DATA)

72-

Ω load on PLLLOCK

0.5

PLLLOCK

Hold time, DATA valid after rising edge of

th(DATA)

72-

Ω load on PLLLOCK

1.5

PLLLOCK

Delay from CLK2 rising edge to PLLLOCK

72-

Ω load on PLLLOCK. Note that PLLLOCK

tdelay(Plllock)

4.5

rising edge

delay increases with a lower impedance load.

Timing Parallel Data Input (External Clock Mode, Latch on PLLLock Falling Edge, CLK2 Clock Input, See Figure 44)

Setup time, DATA valid to falling edge of

ts(DATA)

High impedance load on PLLLOCK

0.5

PLLLOCK

Hold time, DATA valid after falling edge of

th(DATA)

High impedance load on PLLLOCK

1.5

PLLLOCK

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