DAC5687IPZP datasheet(9/72 Pages) TI

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ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)

DAC5687

SLWS164B – FEBRUARY 2005 – REVISED JUNE 2005

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V (= 3.3 V for PLL

Clock Mode), IOVDD = 3.3 V, DVDD = 1.8 V, IOUT

FS = 19.2 mA, External Clock Mode, 4:1 transformer output termination,

50-

Ω doubly terminated load (unless otherwise noted)

AC SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Single carrier, baseband, X4, PLL Clock Mode,

78.4

CLK1 = 122.88 MHz

Single carrier, baseband, X4, PLL Clock Mode,

78.5

CLK2 = 491.52 MHz

Single carrier, IF = 153.6 MHz, X4 CMIX, External Clock

70.9

Mode, CLK2 = 491.52 MHz

Two carrier, IF = 153.6 MHz, X4 CMIX, External Clock

67.8

Mode, CLK2 = 491.52 MHz

Four carrier, baseband, X4, External Clock Mode,

76.1

CLK2 = 491.52 MHz

ACLR(4)

Adjacent channel leakage ratio

dBc

Four carrier, IF = 92.16 MHz, X4L, External Clock Mode,

66.8

CLK2 = 491.52 MHz

Single carrier, IF = 153.6 MHz, X4 CMIX, External Clock

72.2

Mode, CLK2 = 491.52 MHz, DVDD = 2.1 V

Two carrier, IF = 153.6 MHz, X4 CMIX, External Clock

69.3

Mode, CLK2 = 491.52 MHz, DVDD = 2.1 V

Four carrier, baseband, X4, External Clock Mode,

68.5

CLK2 = 491.52 MHz, DVDD = 2.1 V

Four carrier, IF = 92.16 MHz, X4L, External Clock Mode,

66.3

CLK2 = 491.52 MHz, DVDD = 2.1 V

50-MHz offset, 1-MHz BW, Single carrier, baseband,

X4, External Clock Mode, CLK1 = 122.88 MHz

50-MHz offset, 1-MHz BW, Four carrier, baseband,

X4, External Clock Mode, CLK1 = 122.88 MHz

Noise Floor

dBc

50-MHz offset, 1-MHz BW, Single carrier, baseband,

X4, PLL Clock Mode, CLK2 = 491.52 MHz

50-MHz offset, 1-MHz BW, Four carrier, baseband,

X4, PLL Clock Mode, CLK2 = 491.52 MHz

(4)

W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,

DVDD = 1.8 V, IOUT

FS = 19.2 mA (unless otherwise noted)

DIGITAL SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS INTERFACE

VIH

High-level input voltage

VIL

Low-level input voltage

0.8

IIH

High-level input current

–40

µA

IIL

Low-level input current

–40

µA

Input capacitance

IOVDD –

Iload = –100 µA

0.2

VOH

PLLLOCK, SDO, SDIO

0.8 x

Iload = –8 mA

IOVDD

Iload = 100 µA

0.2

VOL

PLLLOCK, SDO, SDIO

0.22 x

Iload = 8 mA

IOVDD

External or dual-clock modes

250

Input data rate

MSPS

PLL clock mode

160

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