LT8551 datasheet(21/32 Pages) AD

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LT8551

Rev 0

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APPLICATIONS INFORMATION

SYNC Pin and Clock Synchronization

The LT8551 has a phase-locked loop (PLL) to synchronize

the internal oscillator to the external clock signal. The

PLL is an edge sensitive digital type that provides zero

degree phase shift between the external clock and internal

oscillators.

To synchronize to an external clock source properly, the

frequency of the external clock source must meet two

criteria listed below:

1. The PLL is guaranteed to work properly only when the

frequency of the external clock source ranges from

125kHz to 1MHz.

2. The external clock can be synchronized to only when

it’s faster than the free-running frequency set by the

RT resistor. If the external clock is lower than fOSC, as

set by RT, the internal oscillator will oscillate at fOSC.

Primary Controller Gate Sensing Filters and Dividers

As has been discussed in the Operation section, the

primary controller’s top and bottom switch states are

detected by the master LT8551 gate sensing pins (i.e.

TGSR, TGSH, TGSL and BGSH). This sensed top gate

signal and bottom gate signal are buffered to the master

LT8551’s TGBUF and BGBUF respectively.

Since the primary controller’s SW node moves fast, an

RC filter RF, CF and bypass capacitor CH must be used,

as shown in Figure 14, to avoid falsely sensing the pri-

mary controller’s top MOSFET’s state. Optional Schottky

clamps close to the TGSL pin of the LT8551 are recom-

mended to prevent the TGSL pin from ringing below

ground or exceeding the pin’s absolute maximum rating if

long traces are used to sense the top gate. Optional filters

are also recommended for both of the primary controller’s

bottom gate sensing and the slave LT8551 devices’ gate

sensing pins, as shown in Figure 14. The time constant

of these filters should be less than 30ns, typical values of

RF = 20Ω, C = 1nF are recommended.

The LT8551 is recommended to work with a primary

controller which has gate driver rail lower than 5.5V. If

the primary has higher than 5.5V gate driver rail, resistor

dividers are required as shown in Figure 15. Use the fol-

lowing equations to design the adequate divider and filter

for the gate sensing or refer to Table 3 for the recom-

mended values:

RF C1C2

+C2

≤ 30ns

CF R5R6

+R6

≤ 30ns

+R2

+R4

+R6

5.5V

Primary's VINTVCC

R1C1

=R2C2

Figure 14.

OPTIONAL

VIN

8551 F14

PRIMARY

CONTROLLER

BST

MASTER

LT8551

TGSR

TGSH

TGSL

BGSH

TGBUF

BGBUF

SLAVE

LT8551

REG

TGSR

TGSH

TGSL

BGSH

Gate Sensing Configuration with Filters

and Schottky Clamps on TGSL

Figure 15.

OPTIONAL

8551 F15

PRIMARY

CONTROLLER

BST

MASTER

LT8551

TGSL

TGSR

TGSH

BGSH

Gate Sensing Configuration when Primary

Gate Driver Rail is Higher than 5.5V

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