LT8551 datasheet(17/32 Pages) AD

17 / 32 page

LT8551

Rev 0

For more information www.analog.com

OPERATION

Current Sensing Gain, Limit and Fault

The gain of five current amplifiers (A0 to A4 in the Block

Diagram) has three gain levels which are set by the ILIM

pin. Connecting the ILIM pin to GND/REG/Floating sets

the gain to 33.3/16.7/11.1, respectively. The outputs of

these amplifiers are called IAMP_INT/IMAP_INTx (in the

Block Diagram). The relation between the IAMP_INT/

IAMP_INTx and the (ISP–ISN)/(ISPx–ISNx) are shown

in Figure 7. There is a 1.4V offset. For expanded channels,

the IAMP_INTx’s value determines the current limit and

current fault as shown in Figure 8.

Figure 7.

–90

2.4

1.4

0.4

8551 F07

–30

–60

ILIM = FLOAT

GAIN = 11.1

ILIM = REG

GAIN = 16.7

IAMP_INT (V)

IAMP_INTx (V)

(ISP – ISN) (mV)

(ISPx – ISNx) (mV)

ILIM = GND, GAIN = 33.3

ILIM = REG, GAIN = 16.7

ILIM = FLOAT, GAIN = 11.1

Current Sensing Amplifier Output Vs. Input

at Three Different Gains

Figure 8.

CURRENT FAULT

CURRENT LIMIT

NORMAL OPERATION

2.8

0.4

2.4

8551 F08

IAMP_INTx Voltage for Current Limit and

Current Fault

When the IAMP_INTx reaches 2.4V but lower than 2.8V,

or if it drops below 0.4V, the corresponding channel

enters current limit. When the current limit condition is

detected, both corresponding channel’s BGx and TGx are

pulled low immediately. The channel resumes switching at

the next clock rising edge after the current limit condition

is removed. The corresponding (ISPx–ISNx) voltages at

current limit are indicated in Figure 7.

When the IAMP_INTx reaches 2.8V, the corresponding

channel enters current fault. When the current fault con-

dition is detected, the corresponding channel enters into

a fault sequence which is described in more detail in the

Fault Sequence section.

Shutdown and Start-Up

Figure 9 illustrates the start-up sequence for the LT8551.

The shutdown pin for the chip is SHDN. When it is driven

below 0.3V, the chip is disabled (chip off state) and qui-

escent current is minimal. Increasing the SHDN voltage

can increase quiescent current but will not enable the chip

until SHDN is driven above 1.15V (typical) after which the

REG LDO is enabled (switcher off state).

Starting up the switching regulator happens after VCC

has risen above 3.55V (typical) and the ENOUT has been

driven above 2.1V (typical). For a master LT8551, the

ENOUT is an open drain pin. When VCC is lower than

3.55V, the ENOUT is pulled to GND to disable switching.

For a slave LT8551, the ENOUT is always a high imped-

ance input pin.

Fault Sequence

The LT8551 activates a fault sequence (see Figure 9)

when IAMP_INTx is higher than 2.8V, which is the fault

condition for a LT8551. The fault event is independent of

channels, which means that the fault condition occurring

in one channel won’t directly affect other channels. If one

of these conditions occurs for a certain channel, the cor-

responding channel’s gate driver outputs are pulled low. If

one of the LT8551’s channels enters latch off mode (see

Figure 9), only restarting the whole chip will reactivate

the channel.

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