OPA835 datasheet(14/21 Pages) TI1

14 / 21 page

Time (150 ns/div)

-0.5

-1.6

-1.2

0.5

-0.8

-0.4

1.5

0.4

2.5

0.8

1.2

3.5

1.6

D090

VIN

Ch-B Out

VSH

Error (%)

D Max

OPA2834

SBOS973 – JUNE 2019

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Typical Applications (continued)

The values of RF and RG depend on multiple factors. Using small resistors in the feedback network helps reduce

output noise and improve measurement accuracy. Small feedback resistors result in a larger power dissipation in

the amplifier output stage. In order to reduce this power dissipation, large-value resistors reduce the phase

margin and cause gain peaking; see Figure 3. Select the values of RF and RG from the recommended range of

values for this device. As given in Equation 4, care must be taken to use a gain resistor value large enough to

limit the current through the input ESD diodes to within 10 mA for a 10-V input transient with the amplifier

powered off a 5-V supply.

where

•

VIN is the input transient voltage

•

VD is the ESD diode forward voltage drop

•

ID is the current resulting from this input transient flowing through the ESD diode

(4)

A total gain of 20 V/V is required from the amplifier stage. An amplifier bandwidth of 5 MHz is needed to drive the

ADS7046 input. Because of this requirement, the two amplifier channels are configured in gains of 5 V/V and 4

V/V respectively. The ADC input common-mode voltage must be biased at mid-supply (that is, 1.8 V). The 0.45-V

reference input to the noninverting input of channel 1 sets its output common-mode voltage to 0.45 V. This

voltage is gained by 4 V/V with channel 2 to give a 1.8-V input common-mode voltage to the ADC. The two

channels of the OPA2834 together provide a signal gain of 20 V/V.

The ADS7046 samples at 1 MSPS with a 40-MHz clock to allow for a sufficient acquisition time for the driver

amplifier settling. The ADS7046, with this setting, exhibits an acquisition time of approximately 625 ns. The driver

amplifier must settle within this time period. Figure 13 shows the TINA simulation plots for channel 2 of the

OPA2834 driving the ADS7046. Here, VIN is the signal swing at the channel noninverting input, CH-B Out is the

signal at the ADC input, VSH is the voltage on the sample-and-hold capacitor internal to the ADC, and error % is

the percent error in VSH from its steady state value. VSH must settle within the acquisition time for the ADC to

digitize the analog-input signal with the required accuracy. The OPA2834 settles to 0.1% accuracy within 500 ns

with a worst-case, 3.6-V full-scale transient output. Using a slower clock with the same sampling rate causes the

ENOB to reduce. This reduction in ENOB is restored with a lower sampling frequency or use of wider bandwidth

amplifiers from the OPA83x family of products.

9.2.1.3 Application Curve

Figure 13. OPA2834 Settling Performance With the ADS7046

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