PD69108/F

Copyright © 2013

Microsemi

Rev. 1.6

Analog Mixed Signal Group

1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308

13

TM

®

Logic Main Control Module

The Logic Main Control Block includes the Digital Timing

Mechanisms and State Machines synchronizing and

activating PoE functions according to MCU control

commands such as:



Real Time Protection (RTP)



Start Up Macro (DVDT)



Load Signature Detection (RES DET)



Classification Macro (CLASS)



Voltage and Current Monitoring Registers (VMC)



ADC Interfacing



Direct Digital Signals with Analog Block

Line Detection Generator

Upon request from the MCU to the Main Control

Module, four different voltage levels are generated by

the Line Detection Generator to ensure a robust AF / AT

Line Detection functionality.

Classification Generator

Upon request from the MCU to the Main Control

Module, the State Machine applies a regulated Class

Event and Mark Event voltage to the ports, as required

by the IEEE standard.

Current Limiter

This circuit continuously monitors the current of powered

ports and limits the current to a specific value, according

to pre-defined limits as set by AF/AT and Current_Set

pins. In cases where the current exceeds this specific

level, the system starts measuring the elapsed time. If

this time period is greater than a preset threshold, the

port is disconnected.

Main MOSFET

Main power switching FET, used to control PoE current

into the load.

ADC

A 10-Bit Analog to Digital converter, used to convert

analog signals into digital registers for the Logic Control

module.

Power on Reset (POR)

Monitors the internal 3.3 V voltage DC levels; if this

voltage drops below specific thresholds, a reset signal is

generated and the PD69108 is reset.

Voltage Regulator

The voltage regulator generates 3.3 VDC and 5 VDC for

the internal circuitry. These voltages are derived from

the Vmain supply.

To use the internal voltage regulator connect:



VAUX5 to DRV_VAUX5



VAUX3P3 to VAUX3P3_INT



REG_EN_N to AGND.

There are two options to reduce the PD69108 power

dissipation by regulating the voltage outside the chip:



Use an external NPN transistor to regulate the

5 VDC.

In this setup, the configuration of the regulators pins

should be:

• DRV_VAUX5 is connected to the NPN BASE

• VAUX5 is connected to the NPN EMITTER

(Connect the Collector to VMAIN)

• VAUX3P3 is connected to VAUX3P3_INT

• REG_EN_N is connected to AGND



Supply the PD69108 with an external 3.3 V voltage

regulator.

In this setup, the configuration of the regulators pins

should be:

• VAUX5 is connected to DRV_VAUX5

• VAUX3P3_INT is connected to VAUX5

• VAUX3P3 is connected to the external 3.3 V

• REG_EN_N is connected to VAUX3P3

The above two options can be implemented

simultaneously.

CLK

CLK is an internal 8 MHz clock oscillator.