PD69108/F

Copyright © 2013

Microsemi

Rev. 1.6

Analog Mixed Signal Group

1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308

10

TM

®

SPI Detailed Timing Information

Name

Min Delay

Max Delay

Description

D1

714ns

SPI clock period

D2

45

55

SPI duty cycle

D3

340 ns

SPI_CS setup to SPI clock Positive Edge (delay after

SPI_CS active signal)

D4

340 ns

SPI_CS hold to SPI clock Positive Edge (delay before

SPI_CS inactive Signal)

D5

2 spi clock cycles

Delay between last SCK in eSPI1 frame and first SCK at

adjacent eSPI1 frame

D6

1 spi clock cycles

Between byte 0 (IC addr) and byte 1(addr)

D7

1 spi clock cycles

Between byte 1 (addr) and byte 2(data).

D8

1 SPI clock cycles

Between byte 2 (MS data byte) and byte 3(LS data byte).

D9

340 ns

MOSI setup time

D10

210 ns

MOSI hold time

D11

140ns

MISO tri-state to valid data from clock positive edge

D12

300ns

MISO valid data to tri-state from SPI_CS positive edge

D13

1 SPI clock cycles

SPI_CS width (Delay eSPI1 frame to adjacent eSPI1 frame)

D14

60ns

Filtered Glitch Width

D15

D3 + 15.5 SPI clock

cycles

D3+23.75 SPI clock

cycles

MISO tri-state from SPI_CS Negative Edge to valid data

D3

D4

D1

D2

D7

D6

D8

D9

D10

CS_N

SCK

MOSI

MISO

D5

D11

D12

D2

SPI1 frame

8 SCK clock cycles

8 SCK clock cycles

8 SCK clock cycles

D13

Noise Spike

D14

D15