ADPD144RI datasheet(21/34 Pages) AD

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Data Sheet

ADPD144RI

Rev. A | Page 21 of 34

OPTIMIZING SNR PER WATT

The ADPD144RI offers a variety of parameters that the user can

adjust to achieve the best signal. One of the key goals of system

performance is to obtain the best system SNR for the lowest

total power, which is often referred to as optimizing SNR per watt.

In systems where SNR is the primary design goal and power is a

secondary concern, there may be a configuration that achieves

the same SNR for an overall lower system power.

Optimizing for Peak SNR

The first step in optimizing for peak SNR is to find a TIA

gain and LED level that gives the best performance where the

number of LED pulses remains constant. It is important to note

that the SNR improves as a square root of the number of pulses

averaged together, whereas LED power consumed is directly

proportional to the number of LED pulses. For every doubling

of the LED pulse count, there is a doubling of the LED power

consumed and a 3 dB SNR improvement. As a result, avoid any

change in the gain configuration that provides less than 3 dB of

improvement for a 2× power penalty. Any TIA gain configuration

that provides more than 3 dB of improvement for a 2× power

penalty is recommended. If peak SNR is the goal and there is no

issue saturating the photodiode with LED current at any gain,

the 50,000 TIA gain setting is an optimal choice. After the SNR

per pulse per channel is optimized, the user can then increase

the number of pulses to achieve the desired system SNR.

Optimizing SNR per Watt in a Signal Limited System

In practice, optimizing for peak SNR is not always practical.

One scenario in which the PPG signal has a poor SNR is the

signal limited regime. In this scenario, the LED current reaches

an upper limit before the desired dc return level is achieved.

Tuning in this case starts where the peak SNR tuning stops. The

starting point is nominally a 50,000 gain, as long as the lowest

LED current setting of 8 mA does not saturate the photodiode

and the 50,000 gain provides enough protection against intense

background light. In these cases, use a 25,000 gain as the

starting point.

The goal of the tuning process is to bring the dc return signal to

a specific ADC range, such as 50% or 60%. The ADC range

choice is a function of the margin of headroom needed to

prevent saturation as the dc level fluctuates over time. The SNR of

the PPG waveform is always some percentage of the dc level. If

the target level cannot be achieved at the base gain, increase the

gain and repeat the procedure. The tuning system may need to

place an upper limit on the gain to prevent saturation from

ambient signals.

Tuning the Pulse Count

After the LED peak current and TIA gain are optimized,

increasing the number of pulses per sample increases the SNR

by the square root of the number of pulses. There are two ways to

increase the pulse count. The pulse count registers (Register 0x31,

Bits[15:8], and Register 0x36, Bits[15:8]) change the number of

pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8],

controls the number of internal samples that are averaged together

before the data is sent to the output. Therefore, the number of

pulses per sample is the pulse count register multiplied by the

number of subsequent samples being averaged. In general, the

internal sampling rate increases as the number of internal

sample averages increase to maintain the desired output data

rate. The SNR per watt is most optimal with pulse count values

of 16 or less. Above pulse count values of 16, the square root

relationship does not hold in the pulse count register. However,

this relationship continues to hold when averaged between

samples using Register 0x15.

Note that increasing the LED peak current increases SNR

almost directly proportional to LED power, whereas increasing

the number of pulses by a factor of nPULSE results in only a

nominal √(nPULSE) increase in SNR.

When using the sample sum and average function (Register 0x15),

the output data rate decreases by the number of summed

samples. To maintain a static output data rate, increase the

sample frequency (Register 0x12) by the same factor as that

selected in Register 0x15. For example, for a 100 Hz output data

rate and a sample sum and average of four samples, set the

sample frequency to 400 Hz.

TIA ADC Mode

The device can be placed in TIA ADC mode, which ties the TIA

directly to the ADC, bypassing the analog ambient light

rejection block. TIA ADC mode provides a relative measure of

the amount of background light present at the input of the device.

This mode only measures dc light and does not measure the

light returned from the LED pulse. To enter TIA ADC mode,

write 0xB065 to Register 0x45 and write 0x0000 to the ADC

offset registers, Register 0x18 through Register 0x21. Increasing

light causes a decrease in the output values because the TIA is

an inverting stage. The data registers then read a relative

amount of dc light. On this device, use TIA ADC mode only as a

relative measurement. This test looks for devices that have a high

resistance between inputs due to solder flux because this

resistance manifests itself as an elevated dc current.

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