ADPD144RI datasheet(13/34 Pages) AD

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Data Sheet

ADPD144RI

Rev. A | Page 13 of 34

ADJUSTABLE SAMPLING FREQUENCY

determines the sampling frequency of the ADPD144RI. The

maximum sampling frequency (fSAMPLE, MAX) is determined by the

sample periods for Time Slot A and Time Slot B plus the

minimum sleep time.

fSAMPLE, MAX = 1/(tA + t1 + tB + t2 + tSLEEP_MIN)

(2)

where tSLEEP_MIN is the minimum sleep time required between

samples.

See the Pulse Timing section for the definitions of tA, t1, tB, and t2.

If a given time slot is not in use, elements from that time slot do

not factor into the calculation. For example, if Time Slot A is

not in use, tA and t1 do not add to the sampling period, and the

maximum sampling frequency is calculated as follows:

fSAMPLE, MAX = 1/(tB + t2 + tSLEEP_MIN)

(3)

External Sync for Sampling

The ADPD144RI provides an option to use an external sync

signal to trigger the sampling periods. This external sample sync

signal is provided on the INT pin. This functionality is

controlled by Register 0x4F, Bits[2:1]. When enabled, a rising

edge on the selected input specifies when the next sample cycle

occurs. When triggered, there is a delay of one to two internal

sampling clock (32 kHz) cycles, and then the normal start-up

sequence occurs. This sequence is the same as if the normal

sample timer provided the trigger. To enable the external sync

signal feature, use the following procedure:

Write 0x1 to Register 0x10 to enter program mode.

Write 1 to Register 0x4F, Bit 2 to select the external sync

using the INT pin. Enable the INT pin input buffer by

writing 1 to Register 0x4F, Bit 1.

Write 0x4000 to Register 0x38.

Write 0x0002 to Register 0x10 to start the sampling

operations.

Apply the external sync signal on the INT pin at the

desired rate (sampling occurs at that rate). As with normal

sampling operations, read the data using the FIFO or the

data registers.

The maximum frequency constraints (fSAMPLE, MAX) still apply

when externally triggering the sample function.

LED Pulse and Sample

At each sampling period, the selected LED driver drives a series

of LED pulses in each time slot as shown in Figure 13. The

magnitude, duration, and number of pulses are programmable

over the I2C interface. Each LED pulse coincides with a sensing

period of the AFE. During the AFE sensing period, the charge

acquired on the photodiode from ambient light is subtracted

from the photodiode charge of the synchronous LED pulse. The

combined signals effectively null the contribution of ambient

light.

During each pulse period, the photodiode output is integrated

and converted to a digital value by the 14-bit ADC. Each

subsequent conversion within a time slot is summed with the

previous result. Up to 255 pulse values from the ADC can be

summed in an individual time slot up to a maximum of 20 bits.

LED DRIVER OPERATION

Integrated LEDs

The ADPD144RI features integrated 660 nm (LED1) and 880 nm

(LED2) LED emitters optimized for SpO2 measurement. The

anodes of the integrated LEDs require connection to a power

supply via the VLED pin, which allows flexibility of the supply

voltage for the LEDs as well as decoupling. A capacitor (CVLED),

placed close to the VLED pin, provides additional pulse current to

the LEDs in pulse mode. Without this capacitor, output impedance

of the LED supply can adversely affect the pulsed performance of

the LEDs. Selection of the correct CVLED value is covered in the

Determining CVLED section.

The LEDX1 and LEDX2 pins are external connections to the

LED drivers and cannot be connected when using the integrated

LED emitters. It is not possible to combine integrated and

external LEDs.

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