ADPD144RI datasheet(18/34 Pages) AD

18 / 34 page

ADPD144RI

Data Sheet

Rev. A | Page 18 of 34

Reading Data from Registers Using Interrupts

The latest sample data is always available in the data registers

and is updated simultaneously at the end of each time slot. The

data value for each photodiode channel is available as a 16-bit

value in Register 0x64 through Register 0x67 for Time Slot A,

and Register 0x68 through Register 0x6B for Time Slot B. If

allowed to reach their maximum value, Register 0x64 through

the unsaturated (up to 27 bits) values for each channel are available

in Register 0x70 through Register 0x77 for Time Slot A and

interrupts are available to indicate when the registers are updated

and can be read. To use the interrupt for a given time slot, use

the following procedure:

1. Enable the sample interrupt by writing a 0 to the appropriate

bit in Register 0x01. To enable the interrupt for Time Slot A,

write 0 to Bit 5. To enable the interrupt for Time Slot B, write 0

to Bit 6. Either or both interrupts can be set. An interrupt is

generated when the data registers are updated.

2. Configure the INT pin by writing the appropriate value to

the bits in Register 0x02.

3. The interrupt handler must perform the following:

a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm

which interrupt has occurred. This step is not

required if only one interrupt is in use.

b. Read the data registers before the next sample can be

written. The system must have an interrupt latency

and service time that is short enough to respond

before the next data update, based on the output data

rate.

c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the

interrupt.

If both time slots are in use, it is possible to use only the

Time Slot B interrupt to signal when all registers can be read. It

is recommended to use the multiword read to transfer the data

from the data registers.

Reading Data from Registers Without Interrupts

If the system interrupt response is not fast or predictable

enough to use the interrupt method, or if the INT pin is not

used, it is possible to obtain reliable data access by using the

data hold mechanism. To guarantee that the data read from the

registers is from the same sample time, it is necessary to prevent

the update of samples while reading the current values.

The method for performing register reads without interrupt

timing is as follows:

1. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_

HOLD bits, Register 0x5F, Bit 1 and Bit 2, respectively, for

the time slot requiring access (both time slots can be

accessed). This write prevents sample updates.

2. Read the registers as desired.

3. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_

DATA_HOLD bits, Register 0x5F, Bit 1 and Bit 2,

respectively. Sample updates are allowed again.

Because a new sample may arrive while the reads are occurring,

this method prevents the new sample from partially overwriting

the data being read.

CLOCKS AND TIMING CALIBRATION

The ADPD144RI uses two internal time bases. A 32 kHz clock

provides master timing for the state machine, sets the sample

timing, and determines the output data rate. A separate 32 MHz

clock controls the digital processing engine of the ASIC. Both

clocks are internally generated and exhibit device to device

variation of approximately 10% (typical).

Both clocks can be calibrated to provide accurate timing for

applications that require precise timing reference.

Calibrating the 32 kHz Clock

The 32 kHz clock provides the coarse timing reference for

sampling time and output data rate. For applications where

an accurate time reference is important, such as heart rate

measurements, calibrate the 32 kHz clock. To calibrate the

clock, take the following steps:

1. Set the sampling frequency to the highest the system can

handle, such as 2000 Hz. Because the 32 kHz clock controls

sample timing, its frequency is readily accessible via the INT

pin. Configure the interrupt by writing 0xC0FF to

frequency by writing 0 to Register 0x01, Bit 5. Monitor the

INT pin. The INT pin then pulses at 1/4 the sample

frequency.

2. If the monitored interrupt frequency × 4 is less than the set

sampling frequency, increase the CLK32K_ADJUST bits,

frequency × 4 is larger than the set sampling frequency,

decrease the CLK32K_ADJUST bits.

Repeat Step 2 until the monitored interrupt signal frequency is

close enough to the set sampling frequency. Note that the

resolution of the 32 kHz clock adjust is 0.6 kHz per LSB.

ADPD144RI датащи(PDF) 18 Page - Analog Devices

ADPD144RI датащи(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL