AD9175 datasheet(62/150 Pages) AD

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AD9175

Data Sheet

Rev. A | Page 62 of 150

Ramp-Up/Ramp-Down Gain Block

A ramp-up/ramp-down gain block is located at the output of

each main datapath and before the samples are routed to the

analog DAC core(s) for decoding. This block is an extension of

the PDP block, and together these blocks protect downstream

components from large signal peaks or sustained average power

that exceeds a user defined threshold.

Various trigger methods can be configured in the PA protection

block to trigger a gain ramp-down to mute the data being

transmitted out of the AD9175, as shown in Figure 78. The

ramp-up and ramp-down steps can be configured via the SPI in

ramp-down occurs in 32 steps over 2(CODE+8) DAC clock periods.

This control can be configured individually for each of the DAC

ramp blocks via the MAINDAC_PAGE control in Register 0x008.

After the data is ramped down due to a trigger event, it can be

ramped back up in two different ways, assuming the trigger event

(error) was cleared. If the SPI protection control bit triggered

the interrupt for a ramp-down, the data can be ramped-up by

toggling Register 0x582, Bit 7 from 0 to 1, and then back to 0.

Alternatively, an option exists to mute the digital data during a

digital clock rotation if the ROTATE_SOFT_OFF_EN control

in Register 0x581, Bit 2 is set to 1. When this bit is set, a

synchronization logic rotation triggers the ramp-up/ramp-down

block to ramp the output down, rotates the digital clocks, and

then ramps the output back up. These actions occur only if Bit 1

of the ROTATION_MODE control in Register 0x03B is set to 1

to enable a datapath clock rotation when the synchronization logic

rotates.

AD9175 датащи(PDF) 62 Page - Analog Devices