AD9175 datasheet(49/150 Pages) AD

49 / 150 page

Data Sheet

AD9175

Rev. A | Page 49 of 150

It is recommended to enable all interrupts that are planned

to be used prior to bringing up the JESD204B link. When

the link is up, the interrupts can be reset and then used to

monitor the link status.

Monitoring Errors via SYNCOUTx±

When one or more disparity, NIT, or unexpected control

character errors occur, the error is reported on the SYNCOUTx±

pin as per Section 7.6 of the JESD204B specification. The

JESD204B specification states that the SYNCOUTx± signal is

asserted for exactly two frame periods when an error occurs. For

the AD9175, the width of the SYNCOUTx± pulse can be

programmed to ½, 1, or 2 PCLK cycles. The settings to achieve a

SYNCOUTx± pulse of two frame clock cycles are given in Table 32.

Table 32. Setting SYNCOUTx± Error Pulse Duration

1 These register settings assert the SYNCOUTx± signal for two frame clock

cycle pulse widths.

Unexpected Control Character, NIT, Disparity IRQs

For UEK character, NIT, and disparity errors, error count over

the threshold events are available as IRQ events. Enable these

events by writing to Register 0x4B8, Bits[7:5]. The IRQ event status

can be read at Register 0x4BA, Bits[7:5] after the IRQs are enabled.

See the Error Counter and IRQ Control section for information

on resetting the IRQ. See the Interrupt Request Operation

section for more information on IRQs.

Errors Requiring Reinitializing

A link reinitialization automatically occurs when four invalid

disparity characters or four NIT characters are received as per

Section 7.1 of the JESD204B specification. When a link

reinitialization occurs, the resync request is at least five frames

and nine octets long.

The user can optionally reinitialize the link when the error

count for disparity errors, NIT errors, or UEK character errors

reaches a programmable error threshold. The process to enable

the reinitialization feature for certain error types is as follows:

Choose and enable which errors to monitor by selecting

them in Register 0x480, Bits[5:3] to Register 0x487,

Bits[5:3]. UEK, BDE, and NIT error monitoring can be

selected for each lane by writing a 1 to the appropriate bit,

as described in Table 33. These are enabled by default.

Write a 0 to the corresponding bit to Register 0x480,

Bits[2:0] to Register 0x487, Bits[2:0] to take counter out of

reset.

Enable the sync assertion mask for each type of error by

writing to SYNC_ASSERT_MASK (Register 0x47D,

Bits[2:0]) according to Table 33.

Program the desired error counter threshold into

ERRORTHRES (Register 0x47C).

For each error type enabled in the SYNC_ASSERT_MASK

programmed threshold, SYNCOUTx± falls, issuing a sync

request. All error counts are reset when a link reinitialization

occurs. The IRQ does not reset and must be reset manually.

Table 33. Sync Assertion Mask (SYNC_ASSERT_MASK)

Addr.

Bit No.

Bit Name

Description

0x47D

BDE

Set to 1 to assert SYNCOUTx±

if the disparity error count

reaches the threshold

NIT

Set to 1 to assert SYNCOUTx±

if the NIT error count reaches

the threshold

UEK

Set to 1 to assert SYNCOUTx±

if the UEK character error

count reaches the threshold

CGS, Frame Sync, Checksum, and ILAS Monitoring

that each stage of the JESD204B link establishment has

occurred.

Bit x of CODE_GRP_SYNC (Register 0x470) is high if Link

Lane x received at least four K28.5 characters and passed code

group synchronization.

Bit x of FRAME_SYNC (Register 0x471) is high if Link Lane x

completed initial frame synchronization.

Bit x of GOOD_CHECKSUM (Register 0x472) is high if the

checksum sent over the lane matches the sum of the JESD204B

parameters sent over the lane during ILAS for Link Lane x. The

parameters can be added either by summing the individual fields

in registers or summing the packed register. The calculated

checksums are the lower eight bits of the sum of the following

fields: DID, BID, LID, SCR, L − 1, F − 1, K − 1, M − 1, N − 1,

SUBCLASSV, NP − 1, JESDV, S − 1, and HD.

Bit x of INIT_LANE_SYNC (Register 0x473) is high if Link

Lane x passed the initial lane alignment sequence.

CGS, Frame Sync, Checksum, and ILAS IRQs

Fail signals for CGS, frame sync, checksum, and ILAS are available

as IRQ events. Enable them by writing to Register 0x4B8,

Bits[3:0]. The IRQ event status can be read at Register 0x4BA,

Bits[3:0] after the IRQs are enabled. Write a 1 to Register 0x4BA,

Bit 0 to reset the CGS IRQ. Write a 1 to Register 0x4BA, Bit 1 to

reset the frame sync IRQ. Write a 1 to Register 0x4BA, Bit 2 to

reset the checksum IRQ. Write a 1 to Register 0x4BA, Bit 3 to

reset the ILAS IRQ.

See the Interrupt Request Operation section for more

information.

PCLK Factor

(Frames/PCLK)

SYNC_ERR_DUR (Register 0x312,

Bits[7:4]) Setting1

0 (default)

1.5

0.5

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