AD9175 datasheet(40/150 Pages) AD

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AD9175

Data Sheet

Rev. A | Page 40 of 150

The AD9175 supports a periodic SYSREF± signal. The periodicity

can be continuous, strobed, or gapped periodic. The SYSREF±

signal can be dc-coupled with a common-mode voltage of 0.6 V

to 2.2 V and differential swing of 200 mV p-p to 1 V p-p. When

dc-coupled, a small amount of common-mode current (up to

0.3 mA) is drawn from the SYSREF± pins. See Figure 63 and

Figure 64 for the SYSREF± internal circuit for dc-coupled and a

c-coupled configurations. Ensure that the SYSREF_INPUTMODE

bit (Register 0x084, Bit 6) is set to 1, dc-coupled, to prevent

overstress on the SYSREF± receiver pins.

10.3kΩ

240F

104Ω

SYSREF–

SYSREF+

104Ω

100Ω

240F

10.3kΩ

130kΩ

VCM

Figure 63. DC-Coupled SYSREF± Receiver Circuitry

10.3kΩ

240F

104Ω

SYSREF–

SYSREF+

104Ω

100Ω

240F

10.3kΩ

130kΩ

VCM

Figure 64. AC-Coupled SYSREF± Receiver Circuitry

To avoid this common-mode current draw, the SYSREF± receiver

can be ac-coupled using a 50% duty cycle periodic SYSREF±

signal with ac coupling capacitors. If ac-coupled, the ac coupling

capacitors combine with the resistors shown in Figure 64 to

make a high-pass filter with an RC time constant of τ = RC.

Select C such that τ > 4/SYSREF± frequency. In addition, the

edge rate must be sufficiently fast to allow SYSREF± sampling

clocks to correctly sample the rising SYSREF± edge before the

next sample clock.

When ac coupling the SYSREF± inputs, ensure that the

SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0,

ac-coupled, to enable the internal receiver biasing circuitry and

prevent overstress on the SYSREF± receiver pins. AC coupling

allows a differential voltage swing from 200 mV to 1 V on the

SYSREF± pins.

SYSREF± Sampling

The SYSREF± signal is sampled by a divide by 4 version of the

DAC clock. Thus, the minimum pulse width of the SYSREF±

signal must exceed 4 DAC clock periods to ensure accurate

sampling. The delay between the SYSREF± and DAC clock

input signal does not need to be timing constrained.

By default, the first SYSREF± rising edge at the SYSREF± inputs

that is detected after asserting the SYSREF_MODE_ONESHOT bit

(Register 0x03A, Bit 1) begins the synchronization and aligns

the internal LMFC signal with the sampled SYSREF± edge.

captured SYSREF± edges are ignored after the SYSREF_MODE_

ONESHOT bit is asserted before the synchronization takes place.

For example, if SYSREF_COUNT is set to 3, the AD9174 does

not sync after the SYSREF_MODE_ONESHOT bit is asserted

until the arrival of the 4th SYSREF± edge.

SYSREF± Jitter IRQ

In Subclass 1, after the one-shot synchronization occurs, the

SYSREF± signal is monitored to ensure that the subsequent

SYSREF± edges do not deviate from the internal LMFC clock

by more than a target amount.

the error window allowed, in DAC clock units. If a SYSREF±

edge varies from the internal LMFC clock by more than the

number of DAC clock units set in SYSREF_ERR_WINDOW,

the IRQ_SYSREF_JITTER is asserted.

Table 24. SYSREF± Jitter Window Tolerance

SYSREF± Jitter Window

Tolerance (DAC Clock Cycles)

SYSREF_ERR_WINDOW

(Register 0x039, Bits[5:0])1

±½

0x00

±4

0x04

±8

0x08

±12

0x0C

±16

0x10

±20

0x14

+24

0x18

±28

0x1C

The two least significant digits are ignored because the SYSREF± signal is

sampled with a divide by 4 version of the DAC clock. As a result, the jitter

window is set by this divide by 4 clock rather than the DAC clock. It is

recommended that at least a four-DAC clock SYSREF± jitter window be

chosen.

The IRQ_SYSREF_JITTER can be configured as described

in the Interrupt Request Operation section to indicate the

SYSREF± signal has varied, and to request the SPI sequence for

a sync be performed again.

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