GD25VE40CSIG datasheet(12/55 Pages) GIGADEVICE

12 / 55 page

Uniform Sector

Dual and Quad Serial Flash

GD25VE40C

the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3

pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#

pins are tied directly to the power supply or ground)

LB bit.

The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control

and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1

individually usin

g the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers

will become read-only permanently.

CMP bit

The CMP bit is a non-volatile Read/Write bits in the Status Register (S14). It is used in conjunction the BP4-BP0 bits

to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The

default setting is CMP=0.

HPF bit

The High Performance Flag (HPF) bit is read only bit, that indicates the status of High Performance Mode (HPM). When

HPF bit is set to 1, it means the device is in High Performance Mode, When HPF bit is set to 0 (default), it means the device

is not in High Performance Mode.

SUS bit

The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend

(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command, software reset (66H+99H)

command as well as a power-down, power-up cycle.

GD25VE40CSIG датащи(PDF) 12 Page - GigaDevice Semiconductor (Beijing) Inc.