GD25VE40CSIG datasheet(34/55 Pages) GIGADEVICE

34 / 55 page

Uniform Sector

Dual and Quad Serial Flash

GD25VE40C

Figure31. Program/Erase Resume Sequence Diagram

7.27.

Erase Security Registers (44H)

The GD25VE40C provides four 256-byte Security Registers which can be read and programmed individually. These

registers may be used by the system manufacturers to store security and other important information separately from the

main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command 

3-byte address on SI CS# goes high. The command sequence is shown in Figure32. CS# must be driven high after the

eighth bit of the last address byte has been latched in, otherwise the Erase Security Registers command is not executed.

As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the

Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is

completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security

Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1,

the Security Registers will be permanently locked; the Erase Security Registers command will be ignored.

Address

A23-A16

A15-A8

A7-A0

Security Registers

00000000

Don’t Care

Figure32. Erase Security Registers command Sequence Diagram

7.28.

Program Security Registers (42H)

The Program Security Registers command is similar to the Page Program command. Each security register contains

one pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch

(WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered

by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon

Command

44H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

Command

7AH

CS#

SCLK

Resume Erase/Program

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