GD25S512MDBJS datasheet(27/87 Pages) GIGADEVICE

27 / 87 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S512MD

7.9. Write Extended Register (C5H)

The Write Extended Register command could be executed no matter the Write Enable Latch (WEL) bit is 0 or 1.The

Write Extended Register instruction is entered by driving CS# low, sending the instruction code “C5H”, and then writing the

Extended Register data Byte as illustrated in Figure 12.

Upon power up or the execution of a Software/Hardware Reset, the Extended Register bit values will be cleared to 0.

Figure 12 Write Extended Register Sequence Diagram

7.10.

Read Data Bytes (READ 03H or 4READ 13H)

The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0), and each bit being latched-in on

the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at

a Max frequency fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is

automatically incremented to the next higher address after each Byte of data is shifted out. The whole memory of single

GD25B256D can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ)

command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is

in progress.

Figure 13 Read Data Bytes Sequence Diagram (ADS=0)

Figure 14 Read Data Bytes Sequence Diagram (ADS=1)

Command

03H

CS#

SCLK

High-Z

9 10

28 29 30 31 32

MSB

34 35 36 37

23 22 21

38 39

24-bit address

MSB

Data Out1

Data Out2

Command

03H

CS#

SCLK

High-Z

9 10

36 37 38 39 40

MSB

42 43 44 45

31 30 29

46 47

32-bit address

MSB

Data Out1

Data Out2

Command

C5H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Extended Addr.

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