GD25S512MDBJS datasheet(26/87 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S512MD

7.7. Write Status Register (WRSR) (01H or 31H or 11H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)

command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S19, S18, S15, S10, S8, S1 and S0 of the Status

Register. CS# must be driven high after the eighth of the data Byte has been latched in. If not, the Write Status Register

(WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose

duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check

the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register

cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (TB, BP3,

BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only.

The Write Status Register-1 (01h) command can also write the Status Register-1&2. To complete the Write Status

Register-1&2 command, the CS# pin must be driven high after the sixteenth bit of data is clocked in. If CS# is driven high

after the eighth clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, and the Status

Figure 10 Write Status Register Sequence Diagram

7.8. Read Extended Register (C8H)

Extended Register contains Address Bit A24. The Read Extended Register instruction is entered by driving CS# low

and shifting the instruction code “C8H” into the SI pin on the rising edge of SCLK. The Extended Register bits are then

shifted out on the SO pin at the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 11.

When the device is in the 4-Byte Address Mode, the value of A24 Bit is ignored.

Figure 11 Read Extended Register Sequence Diagram

Command

01H/31H/11H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Status Register in

Command

C8H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Extended Addr.

MSB

Extended Addr.

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