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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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GD9FS1G8F2AMG датащи(PDF) 9 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD9FS1G8F2AMG датащи(HTML) 9 Page - GigaDevice Semiconductor (Beijing) Inc. |
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9 / 55 page  GD9Fx1GxF2A 9 4.1 PIN DESCRIPTION Signal Name Input/ Output Description R/B# O Ready/Busy ：Open drain output to indicate the target status, low to indicate that one or more operations are in progress. RE# I Read Enable ：Enables serial data output, active low. CE# I Chip Enable ：When high and the target is in the ready state, the target goes into a low-power standby state. When low, the target is selected. CLE I Command Latch Enable ：Enable signal to load a command into the target on the rising edge of WE#, active high. ALE I Address Latch Enable ：Enable signal to load an address into the target on the rising edge of WE#, active high. WE# I Write Enable ：Data, Commands, and Addresses are latched on the rising edge of WE#. WP# I Write Protect ：Low to disable Flash array program and erase operations. IO0 ~ IO7 I/O I/O Port, bits 0-7 ：8-bit wide bidirectional port for transferring address, command, and data to and from the device. IO8 ~ IO15 I/O I/O Port, bits 8-15 ：Upper 8 bits for the 16-bit wide bidirectional port used to transfer data to and from the device. VCC I Power ：Power supply to the device. VSS I Ground ：Power supply ground. NC - No Connection ：Lead is not internally connected. VCC VSS CE# WE# RE# ALE CLE WP# R/B# IO0~IO15 Organization X16 Figure 5_a: GD9Fx1G8F2A figures Figure 5_b: GD9Fx1G6F2A figures VCC VSS CE# WE# RE# ALE CLE WP# R/B# IO0~IO7 Organization X8 |
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