PCD6003 datasheet(59/96 Pages) PHILIPS

59 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6003

12.1.5

DTAM EXTERNAL MEMORY USING DRAM OR ARAM

A standard DRAM or ARAM memory can be connected to the PCD6003 chip as shown in Fig.27. When WR/RD are not

programmed as push-pull outputs, a 1 k

Ω pull-up resistor has to be connected to VDD3V.

handbook, full pagewidth

MBL277

CASN

D[3:0]

A[11:0]

RASN

P3.x

P0[3:0]

MA[7:0]

P2[3:0]

P3.y

PCD6003

ARAM

DRAM

Fig.27 DRAM/ARAM memory connection.

12.2

DTAM external interface during target

debugging

If the DTAM chip is used with the tScope-51 target debug

tool the DTAM chip needs executable SRAM where the

monitor program MON51 can store the program code. This

SRAM is accessible by means of the RD, WR and PSEN

signals. Since connection to parallel flash memory with

XSRAM and ROM is the worst case situation this case is

shown in Fig.28. Since it is not a commercial system

additional logic can be connected to the DTAM chip to

create executable SRAM.

The target debug logic only consists of combinational

logic:

• CENROM ← P2.7, P2.6 or P2.5

• CENFLASH ← P4.3

• CENXSRAM ← (PSEN or not CENROM) and (RD or

not CENFLASH)

• OENXSRAM ← PSEN and RD

• WRXSRAM ← WR.

The port restore logic is necessary to make the MA/P2/P0

ports available for the application.

The MON51 program is assumed to be in the lowest

8 kbytes of the ROM. If the flash memory should be

accessed clear P4.3 to logic 0. Now the MON51 program

has no access to the XSRAM with RD so no breakpoints

are allowed in the code area where P4.3 is logic 0. Set

P4.3 to logic 1 again after the flash memory access to

enable MON51 again to access the XSRAM.

Target debugging requires I2C-bus and one general

purpose input port. This means that at least 31 I/O ports

are available for the application (not using parallel flash)

during target debugging.

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