ACS70310 datasheet(22/27 Pages) ALLEGRO

22 / 27 page

Very High Precision, Programmable Linear Hall-Effect Sensor IC

with Reverse Battery Protection and High-Bandwidth (240 kHz)

Analog Output for Core-Based Current Sensing

ACS70310

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Read (Controller to ACS70310)

The fields for the Read command are:

• Sync (2 zero bits)

• Read/Write (1 bit, must be 1 for read)

• CRC (3 bits)

Figure 18 shows the sequence for a Read command.

Synchronize

MSB

Memory Address

CRC

Read/Write

0 0 1 0/1 0/1 0/1 0/1 0/1 0/1

0/1

0/1 0/1

Figure 18: Read Sequence

Read Acknowledge (ACS70310 to Controller)

The fields for the data return frame are:

• Sync (2 zero bits)

• Data (32 bits):

□ [31:28] Don’t Care

□ [27:26] ECC Pass/Fail

□ [25:0] Data

Figure 19 shows the sequence for a Read Acknowledge. Refer to

the Detecting ECC Error section for instructions on how to detect

Read/Write Synchronize Memory Address Data (32 bits) and

ECC failure.

Synchronize

MSB

Data

(32 bits)

CRC

0 0 0/1 0/1 0/1 0/1

0/1 0/1

0/1

. . .

0/1 0/1

Figure 19: Read Acknowledgement Sequence

Write (Controller to ACS70310)

The fields for the Write command are:

• Sync (2 zero bits)

• Read/Write (1 bit, must be 0 for write)

• Address (6 bits)

• Data (32 bits):

□ [31:26] Don’t Care

□ [25:0] Data

• CRC (3 bits)

Figure 20 shows the sequence for a Write command. Bits [31:26]

are Don’t Care because the ACS70310 automatically generates 6

ECC bits based on the content of bits [25:0]. These ECC bits will

be stored in EEPROM at locations [31:26].

Synchronize

MSB

Memory Address

Data

(32 bits)

CRC

Read/Write

0 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

0/1

. . .

0/1 0/1

Figure 20: Write Sequence

Write Access Code (Controller to ACS70310)

The fields for the Access Code command are:

• Sync (2 zero bits)

• Read/Write (1 bit, must be 0 for write)

• Address (6 bits, address 0x36 for Customer Access)

• Data (32 bits, 0xC4136737 for Customer Access)

• CRC (3 bits)

Figure 21 shows the sequence for an Access Code command.

Synchronize

MSB

Memory Address

Data

(32 bits)

CRC

Read/Write

0 0 0 1 0 0 1 0 0 0/1 0/1 0/1

0/1

. . .

0/1 0/1

Figure 21: Write Access Code

The controller must open the serial communication with the

ACS70310 device by sending an Access Code. It must be sent

within Access Code Timeout, tACC, from power-up, or the device

will be disabled for read and write access.

Access Codes Information

Name

Serial Interface Format

(Hex)

Data (Hex)

Customer

0x36

0xC4136737

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