MAX705ESA datasheet(6/10 Pages) ARTSCHIP

6 / 10 page

MAX705-MAX813L

Low-Cost, µP Supervisory Circuit

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Figure 1. MAX705/MAX706/MAX813L Block Diagram

Figure 2. MAX707/MAX708 Block Diagram

Detailed Description

Reset Output

A microprocessor’s (µP’s) reset input starts the µP in a known

state, whenever the µP is in an unknown state. it should be

held in reset. The MAX705-MAX708/MAX813L assert reset

during power-up and prevent code execution errors during

power-down or brownout conditions.

On power-up, once Vcc reaches 1V, RESET is a guaranteed

logic low of 0.4V or less. AS Vcc rises, RESET stays low.

When Vcc rises above the reset threshold, an internal timer

releases RESET after about 200ms. RESET pulses low

whenever Vcc dips below the reset threshold, i.e. brownout

condition. If brownout occurs in the middle of a previously

initiated reset pulse, the pulse continues for at least another

140ms. On power-down, Once Vcc falls below the reset

threshold, RESET stays low and is guaranteed to be 0.4V or

less until Vcc drops below 1V.

The MAX707/MAX708/MAX813L active-high RESET output is

simply the complement of the RESET output, and is

guaranteed to be valid with Vcc down to 1.1V. Some µPs,

such as Intel’s 80C51, require an active-high reset pulse.

Watchdog Timer

The MAX705/MAX706/MAX813L watchdog circuit monitors

the µP’s activity. If the µP does not toggle the watchdog input

(WDI) within 1.6sec and WDI is not three-stated, WDO goes

low. As long as RESET is asserted or the WDI input is

three-stated, the watchdog time will stay cleared and will not

count. As soon as reset is released and WDI is driven high or

low, the timer will start counting. Pulse as short as 50ns can

be detected.

Typically, WDO will be connected to the non-maskable

interrupt input (NMI) of a µP. When Vcc drops below the reset

threshold, WDO will go low whether or not the watchdog timer

has timed out yet. Normally this would trigger an NMI interrupt,

but RESET goes low simultaneously, and thus overrides the

NMI interrupt.

If WDI is left unconnected, WDO can be used as a low line

output. Since floating WDI disables the internal timer, WDO

goes low only when Vcc falls below the reset threshold, thus

functioning as a low-line output.

The MAX705/MAX706 have a watchdog timer and a RESET

output. The MAX707/MAX708 have both active high and

active-low reset outputs. The MAX813L has both an

active-high reset output and a watchdog timer.

Manual Reset

The manual-reset input (MR) allows reset to be triggered by a

pushbutton switch. The switch is effectively debounced by the

140ms minimum reset pulse width. MR is TTL/CMOS logic

compatible, so it can be driven by an external logic line. MR

can be used to force a watchdog timeout to generate a reset

pulse in the MAX705/MAX706/MAX813L. Simply connect

WDO to MR.

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