MAX705ESA datasheet(5/10 Pages) ARTSCHIP

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MAX705-MAX813L

Low-Cost, µP Supervisory Circuit

www.artschip.com

Pin Description

MAX705/MAX706

MAX707/MAX708

MAX813L

DIP/SO

µMAX

DIP/SO

µMAX

DIP/SO

µMAX

NAME

FUNCTION

Manual-Reset Input triggers a reset pulse when

pulled below 0.8V. This active-low input has an

internal 250µA pull-up current. It can be driven from

a TTL or CMOS logic line as well as shorted to

ground with a switch.

Vcc

+5V Supply Input

GND

0V Ground Reference for all signals

PFI

Power-Fail Voltage Monitor Input. When PFI is less

than 1.25V, PFO goes low. Connect PFI to GND or

Vcc when not nsed.

PFO

Power-Fail Output goes low and sinks current when

PFI is less than 1.25V; otherwise PFO stays high.

WDI

Watchdog Input. If WDI remains high or low for

1.6sec, the internal watchdog timer runs out and

WDO goes low (Figure 1). Floating WDI or

connecting WDI to a high-impedance three-state

buffer disables the watchdog feature. The internal

watchdog timer clears whenever reset is asserted,

WDI is three stated, or WDI sees a rising or falling

edge.

N.C.

No Connect

RESET

Active-Low Reset Output pulses low for 200ms

when triggered, and stays low whenever Vcc is

below the reset threshold (4.65V in the MAX705

and 4.40 V in the MAX706). It remains low for

200ms after Vcc rises above the reset threshold or

MR goes from low to high (Figure 3). A watchdog

timeout will not trigger RESET unless WDO is

connected to MR.

WDO

Watchdog Output pulls low when the internal

watchdog timer finishes its 1.6sec count and does

not go high again until the watchdog is cleared.

WDO also goes low during low-line conditions.

Whenever Vcc is below the reset threshold, WDO

stays low; however, unlike RESET, WDO does not

have a minimum pulse width. As soon as Vcc rise

above the reset threshold, WDO goes high with no

delay.

RESET

Active-High Reset Output is the inverse of RESET.

Whenever RESET is high, RESET is low, and vice

versa (Figure 2). The MAX813L has a RESET

output only.

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