DAC101S101 datasheet(15/19 Pages) NSC

15 / 19 page

1.0 Functional Description (Continued)

was before entering power down. Minimum power consump-

tion is achieved in the power-down mode with SCLK dis-

abled and SYNC and D

IN idled low.

2.0 Applications Information

The simplicity of the DAC101S101 implies ease of use.

However, it is important to recognize that any data converter

that utilizes its supply voltage as its reference voltage will

have essentially zero PSRR (Power Supply Rejection Ratio).

Therefore, it is necessary to provide a noise-free supply

voltage to the device.

2.1 DSP/MICROPROCESSOR INTERFACING

Interfacing the DAC101S101 to microprocessors and DSPs

is quite simple. The following guidelines are offered to has-

ten the design process.

2.1.1 ADSP-2101/ADSP2103 Interfacing

Figure 5 shows a serial interface between the DAC101S101

and the ADSP-2101/ADSP2103. The DSP should be set to

operate in the SPORT Transmit Alternate Framing Mode. It is

programmed through the SPORT control register and should

be configured for Internal Clock Operation, Active Low Fram-

ing and 16-bit Word Length. Transmission is started by

writing a word to the Tx register after the SPORT mode has

been enabled.

2.1.2 80C51/80L51 Interface

A serial interface between the DAC101S101 and the 80C51/

80L51 microcontroller is shown in Figure 6. The SYNC signal

comes from a bit-programmable pin on the microcontroller.

The example shown here uses port line P3.3. This line is

taken low when data is to transmitted to the DAC101S101.

Since the 80C51/80L51 transmits 8-bit bytes, only eight

falling clock edges occur in the transmit cycle. To load data

into the DAC, the P3.3 line must be left low after the first

eight bits are transmitted. A second write cycle is initiated to

transmit the second byte of data, after which port line P3.3 is

brought high. The 80C51/80L51 transmit routine must rec-

ognize that the 80C51/80L51 transmits data with the LSB

first while the DAC101S101 requires data with the MSB first.

2.1.3 68HC11 Interface

A serial interface between the DAC101S101 and the

68HC11 microcontroller is shown in Figure 7. The SYNC line

of the DAC101S101 is driven from a port line (PC7 in the

figure), similar to the 80C51/80L51.

The 68HC11 should be configured with its CPOL bit as a

zero and its CPHA bit as a one. This configuration causes

data on the MOSI output to be valid on the falling edge of

SCLK. PC7 is taken low to transmit data to the DAC. The

68HC11 transmits data in 8-bit bytes with eight falling clock

edges. Data is transmitted with the MSB first. PC7 must

remain low after the first eight bits are transferred. A second

write cycle is initiated to transmit the second byte of data to

the DAC, after which PC7 should be raised to end the write

sequence.

2.1.4 Microwire Interface

Figure 8 shows an interface between a Microwire compatible

device and the DAC101S101. Data is clocked out on the

rising edges of the SCLK signal.

2.2 USING REFERENCES AS POWER SUPPLIES

Recall the need for a quiet supply source for devices that use

their power supply voltage as a reference voltage.

Since the DAC101S101 consumes very little power, a refer-

ence source may be used as the supply voltage. The advan-

tages of using a reference source over a voltage regulator

are accuracy and stability. Some low noise regulators can

also be used for the power supply of the DAC101S101.

Listed below are a few power supply options for the

DAC101S101.

2.2.1 LM4130

The LM4130 reference, with its 0.05% accuracy over tem-

perature, is a good choice as a power source for the

DAC101S101. Its primary disadvantage is the lack of 3V and

5V versions. However, the 4.096V version is useful ifa0to

4.095V output range is desirable or acceptable. Bypassing

the LM4130 VIN pin with a 0.1µF capacitor and the VOUT

pin with a 2.2µF capacitor will improve stability and reduce

output noise. The LM4130 comes in a space-saving 5-pin

SOT23.

20154109

FIGURE 5. ADSP-2101/2103 Interface

20154110

FIGURE 6. 80C51/80L51 Interface

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FIGURE 7. 68HC11 Interface

20154112

FIGURE 8. Microwire Interface

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