1.0 Functional Description

1.1 DAC SECTION

The DAC101S101 is fabricated on a CMOS process with an

architecture that consists of switches and a resistor string

that are followed by an output buffer. The power supply

serves as the reference voltage. The input coding is straight

binary with an ideal output voltage of:

V

where D is the decimal equivalent of the binary code that is

loaded into the DAC register and can take on any value

between 0 and 1023.

1.2 RESISTOR STRING

The resistor string is shown in Figure 3. This string consists

of 4096 equal valued resistors with a switch at each junction

of two resistors, plus a switch to ground. The code loaded

into the DAC register determines which switch is closed,

connecting the proper node to the amplifier. This configura-

tion guarantees that the DAC is monotonic.

1.3 OUTPUT AMPLIFIER

The output buffer amplifier is a rail-to-rail type, providing an

output voltage range of 0V to V

rail types, exhibit a loss of linearity as the output approaches

the supply rails (0V and V

linearity is specified over less than the full output range of the

DAC. The output capabilities of the amplifier are described in

the Electrical Tables.

1.4 SERIAL INTERFACE

The three-wire interface is compatible with SPI, QSPI and

MICROWIRE as well as most DSPs. See the Timing Dia-

gram for information on a write sequence.

A write sequence begins by bringing the SYNC line low.

Once SYNC is low, the data on the D

the 16-bit serial input register on the falling edges of SCLK.

On the 16th falling clock edge, the last data bit is clocked in

and the programmed function (a change in the mode of

operation and/or a change in the DAC register contents) is

executed. At this point the SYNC line may be kept low or

brought high. In either case, it must be brought high for the

minimum specified time before the next write sequence as a

falling edge of SYNC is used to initiate the next write cycle.

Since the SYNC and D

they are high, they should be idled low between write se-

quences to minimize power consumption.

1.5 INPUT SHIFT REGISTER

The input shift register, Figure 4, has sixteen bits. The first

two bits are "don’t cares" and are followed by two bits that

determine the mode of operation (normal mode or one of

three power-down modes). The contents of the serial input

register are transferred to the DAC register on the sixteenth

falling edge of SCLK. See Timing Diagram, Figure 2.

Normally, the SYNC line is kept low for at least 16 falling

edges of SCLK and the DAC is updated on the 16th SCLK

falling edge. However, if SYNC is brought high before the

16th falling edge, the shift register is reset and the write

sequence is invalid. The DAC register is not updated and

there is no change in the mode of operation or in the output

voltage.

1.6 POWER-ON RESET

The power-on reset circuit controls the output voltage during

power-up. Upon application of power the DAC register is

filled with zeros and the output voltage is 0 Volts and remains

there until a valid write sequence is made to the DAC.

1.7 POWER-DOWN MODES

The DAC101S101 has four modes of operation. These

modes are set with two bits (DB13 and DB12) in the control

register.

TABLE 1. Modes of Operation

DB13

DB12

Operating Mode

0

0

Normal Operation

0

1

Power-Down with 1k

Ω to GND

1

0

Power-Down with 100k

Ω to GND

1

1

Power-Down with Hi-Z

When both DB13 and DB12 are 0, the device operates

normally. For the other three possible combinations of these

bits the supply current drops to its power-down level and the

output is pulled down with either a 1k

Ω or a 100KΩ resistor,

or is in a high impedance state, as described in Table 1.

The bias generator, output amplifier, the resistor string and

other linear circuitry are all shut down in any of the power-

down modes. However, the contents of the DAC register are

unaffected when in power-down, so when coming out of

power down the output voltage returns to the same voltage it

20154107

FIGURE 3. DAC Resistor String

20154108

FIGURE 4. Input Register Contents

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