RF64W datasheet(56/76 Pages) HOPE

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ADVANCED COMMUNICATIONS & SENSING

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RF64

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Description

MCParam

Data_mode_x

Defines data operation mode (Æ Packet)

Fifo_size

Defines FIFO size

Fifo_thresh

Defines FIFO threshold

IRQParam

Rx_stby_irq_0

Defines IRQ_0 source in Rx & Stby modes

Rx_stby_irq_1

Defines IRQ_1 source in Rx & Stby modes

Tx_irq_1

Defines IRQ_1 source in Tx mode

Tx_start_irq_0

Defines Tx start condition and IRQ_0 source

RXParam

Sync_size

Defines Sync word size

Sync_tol

Defines the error tolerance on Sync word detection

SYNCParam

Sync_value

Defines Sync word value

PKTParam

Manchester_on

Enables Manchester encoding/decoding

Payload_length

(1)

Length in fixed format, max Rx length in variable format

Node_adrs

Defines node address for Rx address filtering

Pkt_format

Defines packet format (fixed or variable length)

Preamble_size

Defines the size of preamble to be transmitted

Whitening_on

Enables whitening/de-whitening process

CRC_on

Enables CRC calculation/check

Adrs_filt

Enables and defines address filtering

CRC_autoclr

Enables FIFO autoclear if CRC failed

Fifo_stby_access

Defines FIFO access in Stby mode

5.5.9. Packet Mode Example

 Configure all data processing related registers listed below appropriately. In this example we assume CRC is

enabled with autoclear on.

Table 25: Relevant Configuration Registers in Packet Mode (data processing related only)

(1)fixed format only

Tx Mode:

 Program Tx start condition and IRQs: Start Tx when FIFO not empty (Tx_start_irq_0=1) and IRQ_1 mapped to

Tx_done (Tx_irq_1=1)

 Go to Stby mode

 Write all payload bytes into FIFO (Fifo_stby_access=0, Stby interrupts can be used if needed)

 Go to Tx mode. When Tx is ready (automatically handled) Tx starts (Tx_start_irq_0=1).

 Wait for Tx_done interrupt (+1 bit period)

 Go to Sleep mode

Rx Mode:

 Program Rx/Stby interrupts: IRQ_0 mapped to /Fifoempty (Rx_stby_irq_0=10) and IRQ_1 mapped to CRC_OK

(Rx_stby_irq_1=00)



Go to Rx (note that Rx is not ready immediately, see section 7.3.1



Wait for CRC_OK interrupt



Go to Stby



Read payload bytes from FIFO until /Fifoempty goes low. (Fifo_stby_access =1)



Go to Sleep mode

5.5.10. Additional Information

If the number of bytes filled for transmission is greater than the actual length of the packet to be transmitted and

Tx_start_irq_0 = 1, then the FIFO is cleared after the packet has been transmitted. Thus the extra bytes in the

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