RF64W datasheet(34/76 Pages) HOPE

34 / 76 page

ADVANCED COMMUNICATIONS & SENSING

Page 34 of 76

RF64

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5. Data Processing

5.1. Overview

5.1.1. Block Diagram

Figure 25, illustrates the RF64 data processing circuit. Its role is to interface the data to/from the

modulator/demodulator and the uC access points (SPI, IRQ and DATA pins). It also controls all the configuration

registers.

The circuit contains several control blocks which are described in the following paragraphs.

Tx/Rx

RF64

CONTROL

DATA

IRQ_0

IRQ_1

Data

SYNC

RECOG.

PACKET

HANDLER

FIFO

(+SR)

SPI

CONFIG

DATA

NSS_DATA

SCK

MOSI

MISO

Figure 25: RF64

’s Data Processing Conceptual View

The RF64 implements several data operation modes, each with their own data path through the data processing

section. Depending on the data operation mode selected, some control blocks are active whilst others remain

disabled.

5.1.2. Data Operation Modes

The RF64 has three different data operation modes selectable by the user:

 Continuous mode: each bit transmitted or received is accessed in real time at the DATA pin. This mode may be

used if adequate external signal processing is available.

 Buffered mode: each byte transmitted or received is stored in a FIFO and accessed via the SPI bus. uC

processing overhead is hence significantly reduced compared to Continuous mode operation. The packet

length is unlimited.

 Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is

automatically built with preamble, Sync word, and optional CRC, DC free encoding and the reverse operation is

performed in reception. The uC processing overhead is hence reduced further compared to Buffered mode.

The maximum payload length is limited to the maximum FIFO limit of 64 bytes

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