RF64W datasheet(32/76 Pages) HOPE

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ADVANCED COMMUNICATIONS & SENSING

Page 32 of 76

RF64

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For proper operation, the Bit Synchronizer must first receive three bytes of alternating logic value preamble, i.e.

“0101” sequences. After this startup phase, the rising edge of DCLK signal is centered on the demodulated bit.

Subsequent data transitions will preserve this centering.

This has two implications:



Firstly, if the Bit Rates of Transmitter and Receiver are known to be the same, the RF64 will be able to

receive an infinite unbalanced sequen

ce (all “0s” or all ”1s”) with no restriction.



If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the

BitSync can withstand can be estimated as:

This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily

achievable (crystal tolerance is in the range of 50 to 100 ppm).

3.4.12. Alternative Settings

Bit Synchronizer and Active channel filter settings are a function of the reference oscillator crystal frequency, FXTAL.

Settings other than those programmable with a 12.8 MHz crystal can be obtained by selection of the correct

reference oscillator frequency.

3.4.13. Data Output

After OOK or FSK demodulation, the baseband signal is made available to the user on pin 20, DATA, when

Continuous mode is selected.

In Buffered and Packet modes, the data is retrieved from the FIFO through the SPI interface.

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