MPC7455 datasheet(17/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

Electrical and Thermal Characteristics

5.2.2

Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7455 as defined in Figure 4 and Figure 5.

Timing specifications for the L3 bus are provided in Section 5.2.3, “L3 Clock AC Specifications.”

Table 9. Processor Bus AC Timing Specifications 1

At recommended operating conditions. See Table 4.

Parameter

Symbol 2

All Speed Grades

Unit

Notes

Min

Max

Input setup times:

A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], D[0:63],

DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK, TA,

TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL, L3VSEL

tAVKH

tIVKH

tMVKH

2.0

—

Input hold times:

A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], D[0:63],

DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK, TA,

TBEN, TEA, TS,EXT_QUAL, PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL, L3VSEL

tAXKH

tIXKH

tMXKH

—

Output valid times:

A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], WT, CI

D[0:63], DP[0:7]

ARTRY/SHD0/SHD1

BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ]

tKHAV

tKHTSV

tKHDV

tKHARV

tKHOV

—

2.5

Output hold times:

A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], WT, CI

D[0:63], DP[0:7]

ARTRY/SHD0/SHD1

BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ

tKHAX

tKHTSX

tKHDX

tKHARX

tKHOX

0.5

—

SYSCLK to output enable

tKHOE

0.5

—

SYSCLK to output high impedance (all except TS, ARTRY,

SHD0, SHD1)

tKHOZ

—3.5

SYSCLK to TS high impedance after precharge

tKHTSPZ

—1

SYSCLK

3, 4, 5

Maximum delay to ARTRY/SHD0/SHD1 precharge

tKHARP

—1

SYSCLK

3, 5,

6, 7

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