MPC7455 datasheet(23/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 12 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9,

assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.

Table 12. L3 Bus Interface AC Timing Specifications for MSUG2

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades 8

Unit

Notes

L3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1

Min

Max

Min

Max

Min

Max

Min

Max

L3_CLK rise

and fall time

tL3CR,

tL3CF

—1.0

—

1.0

—1.0

Setup times:

Data and

parity

tL3DVEH,

tL3DVEL

– 0.1

—

– 0.1

—

– 0.1

—

– 0.1

—

2, 3,

Input hold

times: Data

and parity

tL3DXEH,

tL3DXEL

tL3_CLK/4

+ 0.30

—tL3_CLK/4

+ 0.30

—tL3_CLK/4

+ 0.30

—tL3_CLK/4

+ 0.30

—ns

2, 4

Valid times:

Data and

parity

tL3CHDV,

tL3CLDV

—(– tL3_CLK/4)

+ 0.60

—(– tL3_CLK/4)

+ 0.40

—(– tL3_CLK/4)

+ 0.20

—(– tL3_CLK/4)

+ 0.00

5, 6,

Valid times:

All other

outputs

tL3CHOV

—tL3_CLK/4

+ 0.80

—tL3_CLK/4

+ 0.60

—tL3_CLK/4

+ 0.40

—tL3_CLK/4

+ 0.20

5, 7

Output hold

times: Data

and parity

tL3CHDX,

tL3CLDX,

tL3_CLK/4

– 0.40

—tL3_CLK/4

– 0.60

—tL3_CLK/4

– 0.80

—tL3_CLK/4

– 1.00

—ns

5, 6,

Output hold

times: All

other outputs

tL3CHOX

tL3_CLK/4

– 0.20

—tL3_CLK/4

– 0.40

—tL3_CLK/4

– 0.60

—tL3_CLK/4

– 0.80

—ns

5, 7

L3_CLK to

high

impedance:

Data and

parity

tL3CLDZ

—tL3_CLK/2

—

tL3_CLK/2

—

tL3_CLK/2

—

tL3_CLK/2

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