RFM219SW datasheet(30/35 Pages) HOPE

30 / 35 page

RFM219SW

www.hoperf.com

Rev 1.0 | Page 30/35

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PREAM_PS_FLG

This interrupt is generated when the preamble validation is passed and

the PREAM_PS_EN is set to 1. It can be cleared by setting the

PREAM_PS_CLR to 1.

SYNC_PS_FLG

This interrupt is generated when the sync word validation is passed and

the SYNC_PS_EN is set to 1. It can be cleared by setting the

SYNC_PS_CLR to 1.

NODE_PS_FLG

This interrupt is generated when the node ID validation is passed in the

packet mode and the NODE_PS_EN is set to 1. It can be cleared by

setting the NODE_PS_CLR to 1.

CRC_PS_FLG

This interrupt is generated when the CRC validation is passed in the

packet mode and the CRC_PS_EN is set to 1. It can be cleared by

setting the CRC_PS_CLR to 1.

PKT_DONE_FLG

This interrupt is generated when a packet is received (regardless of the

CRC validation) in the packet mode and the PKT_DONE_EN is set to 1.

It can be cleared by setting the PKT_DONE_CLR to 1.

Table 22. INTCTL_D

Bit

Bit Name

Descriptions

RESV

This bit is reserved.

This interrupt is generated in the FIFO Mode and Packet Mode. The flag

INTCTL_D

(0x44)

FIFO_FULL_FLG

FIFO_NMTY_FLG

FIFO_TH_FLG

FIFO_OVF_FLG

FIFO_PKT_CLR

goes high when the FIFO is full. It is cleared automatically when the

FIFO is not full.

This interrupt is generated in the FIFO Mode and Packet Mode. The flag

goes high when the FIFO is found to be not empty (the number of

unread data byte is not zero). It is cleared automatically when the FIFO

is empty.

This interrupt is generated in the FIFO Mode and Packet Mode. The flag

goes high when the number of unread data bytes reaches/exceeds the

value defined in the “FIFO Threshold” parameter. It is cleared

automatically when the number of unread data bytes is less than the

“FIFO Threshold”.

This interrupt is generated in the FIFO Mode and Packet Mode. The flag

goes high when the FIFO is overflow. It is cleared automatically when

the FIFO is not overflow.

0: Keep the FIFO content (default).

1: Clear the FIFO content.

Note: This bit only takes effect in the STBY, TUNE, RX and EEPROM

state. In the SLEEP state, the FIFO and packet handler is automatically

cleared and reset.

r/w

RESV

Must always set to 0.

r/w

RESV

Must always set to 0.

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