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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RFM219SW датащи(PDF) 27 Page - HOPE Microelectronics CO., Ltd. |
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RFM219SW датащи(HTML) 27 Page - HOPE Microelectronics CO., Ltd. |
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27 / 35 page  RFM219SW www.hoperf.com Rev 1.0 | Page 27/35 E-mail:sales@hoperf.com Register that has the address 0x47 allows the user to set and verify the operation modes. Register that has the address 0x4F is dedicated to the soft reset command. Table 16. Control Bank Registers Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INT_EN 0x3F 0x00 SL_TMO_EN RX_TMO_EN RSSI_VLD_EN PREM_PS_EN NODE_PS_EN SYNC_PS_EN CRC_PS_EN PKT_DONE_EN IO_SEL 0x40 0x00 GPO4_SEL<1:0> GPO3_SEL<1:0> GPO2_SEL<1:0> GPO1_SEL<1:0> INTCTL_A 0x41 0x00 INT2_CTL<3:0> INT1_CTL<3:0> INTCTL_B 0x42 0x00 SL_TMO_CLR RX_TMO_CLR RSSI_VLD_CLR PREM_PS_EN NODE_PS_CLR SYNC_PS_CLR CRC_PS_CLR PKT_DONE_CLR INTCTL_C 0x43 0x00 SL_TMO_FLG RX_TMO_FLG RSSI_VLD_FLG PREM_PS_FLG NODE_PS_FLG SYNC_PS_FLG CRC_PS_FLG PKT_DONE_FLG INTCTL_D 0x44 0x00 RESV FIFO_FULL_FLG FIFO_NMTY_FLG FIFO_TH_FLG FIFO_OVF_FLG FIFO_PKT_CLR RESV RESV RSSI 0x45 0x00 RSSI_VALUE<7:0> FUNC_EN 0x46 0x04 RESV SLTIMER_STOP PROD_TEST_EN RESV RESV HS_SPI_EN RESV RESV OP_CTRL 0x47 0x00 OP_STATUS<2:0> OP_SW ITCH<4:0> SOFTRST 0x4F NA SOFT_RST<7:0> The detailed descriptions of each register are given below. Table 17. INT_EN Register Register Bit RW Bit Name Descriptions 0: Disable the sleep timer timeout interrupt (default). INT_EN (0x3F) 7 r/w SL_TMO_EN 6 r/w RX_TMO_EN 5 r/w RSSI_VLD_EN 4 r/w PREAM_PS_EN 3 r/w SYNC_PS_EN 2 r/w NODE_PS_EN 1 r/w CRC_PS_EN 0 r/w PKT_DONE_EN 1: Enable the sleep timer timeout interrupt. 0: Disable the receive timer timeout interrupt (default). 1: Enable the receive timer timeout interrupt. 0: Disable the RSSI valid interrupt (default). 1: Enable the RSSI valid interrupt. 0: Disable the preamble detection pass interrupt (default). 1: Enable the preamble detection pass interrupt. 0: Disable the sync word detection pass interrupt (default). 1: Enable the sync word detection pass interrupt. 0: Disable the node ID detection pass interrupt (default). 1: Enable the node ID detection pass interrupt. 0: Disable the CRC validation pass interrupt (default). 1: Enable the CRC validation pass interrupt. 0: Disable the packet receive finish interrupt (default). 1: Enable the packet receive finish interrupt. |
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