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MSM548331

18/23

RCLK

N CYCLE

(N-1)CYCLE

(N-2)CYCLE

(N+2) CYCLE

(N+1) CYCLE

Low

RADE/RX

—

—

RR

Valid

D(N+1)

—

—

—

—

RXINC

—

—

RE

—

—

DO0 - 11

—

—

OE

—

—

—

—

—

—

—

—

—

—

—

—

Low

Low

Valid

D(N+2)

Valid

D(N-1)

Valid

D(N)

Valid

D(N-3)

Valid

D(N-2)

High

Valid

D(N+2)

High-Z

Valid

D(N+3)

Valid

D(N-1)

Valid

D(N)

Valid

D(N-3)

Valid

D(N-2)

—

—

—

—

N CYCLE

(N-1)CYCLE

(N-2)CYCLE

(N+3) CYCLE

(N+2) CYCLE

Low

Low

Low

High

RCLK

RADE/RX

RR

RXINC

OE

DO0 - 11

RE

,



Read Cycle (RE Control)

Note : In the cycle of OE = "L", the read address pointer is incremented and the output enters the high

impedance state.

Note : In the cycle of RE = "L", the read address pointer is not incremented and the data at the address

is output continuously.

Read Cycle (OE Control)