¡ Semiconductor

MSM548331

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PIN FUNCTION

READ RELATED

RCLK : Read Clock

RCLK is the read control clock input. Synchronized with RCLK's rising edge, serial read access from

read ports is executed when both RE and OE are high.

The internal counter for the serial read address is incremented automatically on the rising edge of

RCLK. In a read address set cycle, all the read address bits which were input from RXAD pin are

stored into internal address registers synchronized with RCLK. In this address set cycle, RADE/RX

must be held high and RR must be held low.

In the read address reset cycle, various read address reset modes can be set synchronously with

RCLK. These reset cycles work to replace complicated serial address control which requires many

RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates

memory access.

RE : Read Enable

RE is a read enable clock input. RE enables or disables both internal read address pointers and data-

out buffers. When RE is high, the internal read address pointer is incremented synchronously with

RCLK. When RE is low, even if the RCLK is input, the internal read address pointer is not

incremented.

OE : Output Enable

OE is an output enable clock input. OE enables or disables data-outs. OE high level enables the

outputs. The internal read address pointer is always incremented by cycling RCLK regardless of OE

level.

DO0-11 : Data-Outs

DO0-11 are serial data-outs. Data is output synchronously with RCLK when OE is high. The output

enable/disableoperationthroughOEinputisperformedsynchronouslywithOEandasynchronously

with RCLK.

RR : Read Reset

RR is a read reset control input. Read address reset modes are defined when RR level is high

according to the "FUNCTION TABLE for read".

RXINC : Read X Address Increment

RXINC is a read X address (or line address) increment control input. In the read address reset cycle,

defined by RR high, the X address (or line address) is incremented by 1 when RXINC is pulled high

with RADE/RX low.

RADE/RX : Read Address Enable/Read X Address Reset Logic Function

RADE/RX is a dual function control input. RADE, one of the two functions of RADE/RX, is a read

address enable input. In the read address set cycle, defined by RR high, X address (or line address)

input from the RXAD pin are latched into internal read X address register synchronously with RCLK.

RX, the second function of RADE/RX, works as an element to set read X address (or line address)

reset mode. In an address reset mode cycle, defined by RR high, read X address is reset to 0 when

RADE/RX is pulled high with RXINC low.

RXAD : Read X Address

RXAD is a read X address (or line address) input. RXAD specifies the line address. 9 bits of read X

address data are input serially from RXAD.