ZXLD1370

Document number: DS32165 Rev. 6 - 2

7 of 40

www.diodes.com

December 2016

© Diodes Incorporated

ZXLD1370

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Output Parameters

FLAG Pin Low Level Output Voltage

Output sinking 1mA

—

—

0.5

V

FLAG Pin Open Drain Leakage Current

—

—

1

µA

STATUS Flag No-Load Output Voltage

(Note 12)

Normal Operation

4.2

4.5

4.8

V

(Note 13)

3.3

3.6

3.9

3.3

3.6

3.9

3.3

3.6

3.9

1.5

1.8

2.1

Excess Sense Resistor Current

0.6

0.9

1.2

Output Impedance of STATUS Output

Normal Operation

—

10

—

kΩ

Driver Output (PIN GATE)

High Level Output Voltage

No Load Sourcing 1mA

(Note 14)

9.5

11

—

V

4

5.5

—

Low Level Output Voltage

Sinking 1mA, (Note 15)

—

—

0.5

V

High Level GATE CLAMP Voltage

—

12.8

15.0

V

Dynamic peak current available during rise

or fall of output voltage

Charging or Discharging Gate of External

—

±300

—

mA

Time to assert ‘STALL’ flag and warning on

STATUS output (Note 16)

GATE low or high

—

100

170

µs

Upper Threshold Voltage

Onset of Output Current Reduction

560

625

690

mV

Lower Threshold Voltage

Output Current Reduced to <10% of Set

380

440

500

mV

—

—

1

µA

Notes:

12. In the event of mor

e than one fault/warning condition occurring, the higher priority condition will take precedence. E.g. ‘Excessive coil current’ and

‘Out of regulation’ occurring together will produce an output of 0.9V on the STATUS pin. The voltage levels on the STATUS output assume the

minimum value of 6V.

internally to prevent it exceeding 15V. Below 12V the minimum gate pin voltage will be 2.5V below Vaux.

15. GATE is switched to PGND by an NMOS transistor

grounded internally and the SHP pin is switched to its nominal operating voltage, before operation is allowed to resume. Restart cycles will be

until normal operation is possible.