LTC2616CDD datasheet(15/20 Pages) LINER

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LTC2606/LTC2616/LTC2626

26061626f

OPERATIO

1ST DATA BYTE

Input Word (LTC2606)

Write Word Protocol for LTC2606/LTC2616/LTC1626

D13

D14

D15

SLAVE ADDRESS

1ST DATA BYTE

D12 D11 D10 D9

D7 D6

D1 D0

2ND DATA BYTE

3RD DATA BYTE

2606 F03

2ND DATA BYTE

INPUT WORD

3RD DATA BYTE

1ST DATA BYTE

Input Word (LTC2616)

D11

D12

D13

D10 D9

D5 D4

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

Input Word (LTC2626)

D10

D11

D3 D2

2ND DATA BYTE

3RD DATA BYTE

a high impedance state, and the output pin is passively

pulled to ground through 90k resistors. Input- and DAC-

The DAC channel can be put into power-down mode by

using command 0100b. The 16-bit data word is ignored.

The supply and reference currents are reduced to almost

zero when the DAC is powered down; the effective

resistance at REF becomes a high impedance input

(typically > 1GΩ).

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 2

or performing an asychronous update (LDAC) as de-

scribed in the next section. The DAC is powered up as its

voltage output is updated. When the DAC in powered-

down state is powered up and updated, normal settling is

delayed. The main bias generation circuit block has been

Figure 3

automatically shut down in addition to the DAC amplifier

and reference input and so the power up delay time is

12µs (for VCC = 5V) or 30µs (for VCC = 3V)

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 2, the

LDAC pin asynchronously updates the DAC register with

the contents of the input register. Asynchronous update is

disabled when the input word is being clocked into the part.

If a complete input word has been written to the part, a low

on the LDAC pin causes the DAC register to be updated

with the contents of the input register.

If the input word is being written to the part, a low going

pulse on the LDAC pin before the completion of three bytes

of data powers up the DAC but does not cause the output

to be updated. If LDAC remains low after a complete input

word has been written to the part, then LDAC is recog-

nized, the command specified in the 24-bit word just

transferred is executed and the DAC output is updated.

The DAC is powered up when LDAC is taken low, indepen-

dent of any activity on the I2C bus.

If LDAC is low at the falling edge of the 9th clock of the 3rd

byte of data, it inhibits any software power-down com-

mand that was specified in the input word.

Table 2

COMMAND*

0000

Write to Input Register

0001

Update (Power Up) DAC Register

0011

Write to and Update (Power Up)

0100

Power Down

1111

No Operation

*Command codes not shown are reserved and should not be used.

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