LTC2616CDD datasheet(14/20 Pages) LINER

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LTC2606/LTC2616/LTC2626

26061626f

OPERATIO

Table 1. Slave Address Map

CA2

CA1

CA0

GND

FLOAT

GND

VCC

001

010

GND

FLOAT

GND

FLOAT

GND

FLOAT

VCC

010

001

GND

VCC

GND

010

GND

VCC

FLOAT

GND

VCC

011

000

FLOAT

GND

FLOAT

GND

FLOAT

GND

VCC

011

FLOAT

GND

FLOAT

VCC

100

010

FLOAT

VCC

GND

100

011

FLOAT

VCC

FLOAT

VCC

101

001

VCC

GND

VCC

GND

FLOAT

VCC

GND

VCC

110

000

VCC

FLOAT

GND

VCC

FLOAT

VCC

FLOAT

VCC

110

011

VCC

GND

111

000

VCC

FLOAT

VCC

111

010

GLOBAL ADDRESS

In addition to the address selected by the address pins, the

parts also respond to a global address. This address

allows a common write to all LTC2606, LTC2616 and

LTC2626 parts to be accomplished with one 3-byte write

transaction on the I2C bus. The global address is a 7-bit

on-chip hardwired address and is not selectable by CA0,

CA1 and CA2.

The addresses corresponding to the states of CA0, CA1

and CA2 and the global address are shown in Table 1. The

maximum capacitive load allowed on the address pins

(CA0, CA1 and CA2) is 10pF, as these pins are driven

during address detection to determine if they are floating.

Write Word Protocol

The master initiates communication with the LTC2606/

LTC2616/LTC2626 with a START condition and a 7-bit slave

address followed by the Write bit (W) = 0. The LTC2606/

LTC2616/LTC2626 acknowledges by pulling the SDA pin

low at the 9th clock if the 7-bit slave address matches the

address of the parts (set by CA0, CA1 and CA2) or the global

address. The master then transmits three bytes of data. The

LTC2606/LTC2616/LTC2626 acknowledges each byte of

data by pulling the SDA line low at the 9th clock of each data

byte transmission. After receiving three complete bytes of

data, the LTC2606/LTC2616/LTC2626 executes the com-

mand specified in the 24-bit input word.

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2606/LTC2616/LTC2626 do

not acknowledge the extra bytes of data (SDA is high

during the 9th clock).

The format of the three data bytes is shown in Figure 3. The

first byte of the input word consists of the 4-bit command

and four don’t care bits. The next two bytes consist of the

16-bit data word. The 16-bit data word consists of the

16-, 14- or 12-bit input code, MSB to LSB, followed by 0,

2 or 4 don’t care bits (LTC2606, LTC2616 and LTC2626

respectively). A typical LTC2606 write transaction is shown

in Figure 4.

The command assignments (C3-C0) are shown in Table 2.

The first four commands in the table consist of write and

update operations. A write operation loads a 16-bit data

word from the 32-bit shift register into the input register.

In an update operation, the data word is copied from the

input register to the DAC register and converted to an ana-

log voltage at the DAC output. The update operation also

powers up the DAC if it had been in power-down mode. The

data path and registers are shown in the Block Diagram.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever the DAC

output is not needed. When in power-down, the buffer

amplifier, bias circuit and reference input is disabled and

draws essentially zero current. The DAC output is put into

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